Bipolar inverter and its use in a logic circuit

Claim 2

A bipolar inverter circuit comprising, at least a single bipolar switchable transistor (3), a first region (6) of which is connected to a given potential and a second region of which is connected to a potential (+V o ) different from said given potential, a load device (2) interposed between said potential different from said given potential and said second region, an output terminal (4) connected to said second region and said load device, an input terminal (15) connected to a third region (8) of said transistor (3), characterized by a source (10) of standby current of one polarity connected to said third region (8) of said transistor (3) for maintaining said transistor in a conductive state when rendered conductive by a signal applied to said input terminal (15), means (12) connected between said source (10) of standby current and said input terminal (15) for shunting said source to said given potential when said transistor is rendered nonconductive by another signal applied to said input and, means (14) connected to said third region (8) of said transistor (3) and said input terminal (15) for augmenting said standby current when said signal is applied to said input terminal.

Claim 3

An inverter circuit, as claimed in claim 1, characterized in that said first region (6) is the emitter of said transistor,said second region is the collector of said transistor and said third region (8) is the base of said transistor.

Claim 4

An inverter circuit as claimed in claim 1, characterized in that said load device is another bipolar switchable transistor (3).

Claim 5

An inverter circuit as claimed in claim 1, characterized in that said means for shunting said source to said given potential is a diode (12) which is rendered conductive by the application of said another signal to said input.

Claim 6

An inverter circuit as claimed in claim 1, characterized in that said means (14) for augmenting said standby current of one polarity is a capacitor, the charge on which is changed when said transistor is rendered conductive.

Claim 7

An inverter circuit as claimed in claim 2, characterized in that the diode formed by said base (8) and said emitter (6) of said transistor (3) has a given switching point and said transistor has a given input capacitance.

Claim 8

An inverter circuit as claimed in claim 3, characterized in that said another bipolar switchable transistor (2) is the complement of said switchable transistor (3) and wherein a first region (5) of said another bipolar switchable transistor is connected to said potential (+V 0 )-different from said given potential, a second region of said another bipolar switchable device is connected to said output terminal (4) and a third region (7) of said another bipolar device is connected to said input terminal (15), a source (9) of standby current of a second polarity connected to said third region (7) of said another transistor (2) for maintaining said another transistor in a conductive state when rendered conductive by said another signal applied to said input terminal (15), means (11) connected between said source (9) of standby current of a second polarity and said input terminal for shunting said source of standby current of a second polarity to the potential level of said signal when said another transistor is rendered nonconductive by said signal applied to said input, and, means (13) connected to said third region of said another transistor and said input terminal for augmenting said standby current of second polarity when said another signal is applied to said input terminal.

Claim 9

An inverter circuit as claimed in claim 6, characterized in that said diode (12) has a switching point which is lower than said given switching point of said diode formed by said base and said emitter of said transistor (3).

Claim 10

An inverter circuit as claimed in claim 6, characterized in that said capacitor (13) has a capacitance greater than said given input capacitance of said transistor (3).

Claim 11

The use of the inverter circuit as claimed in any of the preceding claims in a logic circuit, characterized by a first pair of bipolar switchable transistors (21, 22) connected in series a first region of one of said first pair being connected to a given potential (O V ), a second pair of bipolar switchable transistors (23, 24) which are the complements of said first pair of transistors connected in parallel, first region of which are connected to a potential (+V O ) different from said given potential and second region of which are connected to a second region of another of said first pair, a first region of said another of said first pair being connected to a second region of said one of said first pair, an output terminal (25) connected to said second regions of said second pair of transistors and to said second region of said another of said first pair, a first input terminal (29) connected to a third region of one (21) of said first pair of transistors and to a third region of one (24) of said second pair of transistors, a second input terminal (30) connected to a third region of another (22) of said first pair of transistors and to a third region of another (23) of said second pair of transistors, a source (26) of standby current of a first polarity connected to each of said third regions of said first pair of transistors (21, 22) for maintaining said transistors in a conductive state when rendered conductive by a signal applied to said first and second input terminals (29, 30), a source (26) of standby current of a second polarity connected to each of said third regions of said second pair of transistors (24, 23) for maintaining said transistors in a conductive state when rendered conductive by another signal applied to said first and second input terminals (29, 30), means (31, 27) connected between each of said sources (26, 28) of standby current and said input terminals (29, 30) for shunting said sources of standby current of said first and second polarity to said given potential and to said level of said signal, respectively, when said first and second pairs of transistors are rendered nonconductive by said another signal and said signal, respectively, applied at said inputs, and, means (32, 28) connected in parallel with each said means (31, 27) for shunting for augmenting said standby current of one polarity and said standby current of second polarity when said signal and said another signal are applied to said third regions of said first and second pairs of transistors, respectively.