EP0021831A1 — Pixel clock circuit and method of operating a ras…

Claim 1

Independent Claim 174 words

A clock circuit for producing pixel clock pulses for use in clocking out video image signals to the scanning beam modulator (14) of a raster imaging device having detector means (38,39) for generating signals defining start and end of scan of said scanning beam, characterized by: a clock gate (70) having an inherent operating time delay; means (63) to input said start and end of scan signals to one input of said clock gate, the output of said clock gate comprising said pixel clock pulses; a feedback loop for feeding pixel clock pulses output by said clock gate to said clock gate input; adjustable signal delay means (72) in said feedback loop, the sum of said clock gate time delay and said adjustable signal delay means determining oscillation frequency of said clock gate; and control means responsive to changes in velocity of said scanning beam for regulating said adjustable signal delay means to control the frequency of the pixel clock pulses output by said clock gate in response to variations in scanning beam velocity.

Claim 2

Dependent Claim 174 words

A clock circuit for producing pixel clock pulses for use in clocking out video image signals to the scanning beam modulator (14) of a raster imaging device having detector means (38,39) for generating signals defining start and end of scan of said scanning beam, characterized by: a clock gate (70) having an inherent operating time delay; means (63) to input said start and end of scan signals to one input of said clock gate, the output of said clock gate comprising said pixel clock pulses; a feedback loop for feeding pixel clock pulses output by said clock gate to said clock gate input; adjustable signal delay means (72) in said feedback loop, the sum of said clock gate time delay and said adjustable signal delay means determining oscillation frequency of said clock gate; and control means responsive to changes in velocity of said scanning beam for regulating said adjustable signal delay means to control the frequency of the pixel clock pulses output by said clock gate in response to variations in scanning beam velocity.

Claim 3

Dependent Claim 69 words

The clock circuit according to claim 1 further characterized by: means (70,74,75) for generating a first timing pulse reflecting the interval required to process a preselected number of pixels at existing pixel clock pulse frequency; means (62) for generating a second timing pulse reflecting the interval between start-of-scan and end-of-scan; and comparator means (61) for adjusting said pixel clock frequency in response to said first and second timing pulses.

Claim 4

Dependent Claim 75 words

The clock circuit according to claim 1 further characterized by: counter means (58) programmed to a preselected count representing the number of pixels in a scan line; a feedback loop (59) for feeding pixel clock pulses output by said clock gate to said counter means, said counter means generating an output pulse having a width representative of the time interval required to process said preselected pixel count at existing pixel clock frequency; phase comparator means

Claim 5

Dependent Claim 82 words

(61); means to feed said counter means output pulse to said phase comparator means; means (63) to input a scan pulse having a width defined by start-of-scan and end-of-scan signals; said phase comparator means comparing the phase relation of said counter means output pulse with said scan pulse and generating a phase signal reflecting differences between said pulses; and frequency adjusting means (90) for adjusting the response time of said gate and said pixel clock frequency in response to said phase signal.

Claim 6

Dependent Claim 82 words

(61); means to feed said counter means output pulse to said phase comparator means; means (63) to input a scan pulse having a width defined by start-of-scan and end-of-scan signals; said phase comparator means comparing the phase relation of said counter means output pulse with said scan pulse and generating a phase signal reflecting differences between said pulses; and frequency adjusting means (90) for adjusting the response time of said gate and said pixel clock frequency in response to said phase signal.

Claim 7

Independent Claim 160 words

The method of operating a raster scanner of the type having a scanning beam (11) to illuminate a photosensor (25) in response to image pixel signals to form a latent electrostatic image thereon, with modulator means (14) for controlling exposure of said photosensor by said beam, and clock means for producing pixel clock pulses for clocking image pixel signals to said modulator, characterized by: generating (70,72) a first signal pulse having a duration that is a function of the time required to process a preselected number of image pixel signals across the scan line at the pixel clock rate of the preceding line; generating (38,39,62) a second signal pulse having a duration that is a function of the interval between start of scan and end of scan; comparing (61) the phase relationship of said first and second signal pulses; and adjusting (90) the output frequency of said clock means to minimize any phase difference between said first and second signals.

Claim 8

Independent Claim 160 words

The method of operating a raster scanner of the type having a scanning beam (11) to illuminate a photosensor (25) in response to image pixel signals to form a latent electrostatic image thereon, with modulator means (14) for controlling exposure of said photosensor by said beam, and clock means for producing pixel clock pulses for clocking image pixel signals to said modulator, characterized by: generating (70,72) a first signal pulse having a duration that is a function of the time required to process a preselected number of image pixel signals across the scan line at the pixel clock rate of the preceding line; generating (38,39,62) a second signal pulse having a duration that is a function of the interval between start of scan and end of scan; comparing (61) the phase relationship of said first and second signal pulses; and adjusting (90) the output frequency of said clock means to minimize any phase difference between said first and second signals.

Claim 9

Dependent Claim 47 words

The method according to claim 4 further characterized by: clocking out at the pixel clock rate of the preceding scan line the total number of pixels for the scan line being processed; and measuring the interval required to clock out said pixels to provide said first signal.

Claim 10

Dependent Claim 45 words

The method according to claim 4 or 5 further characterized by: changing the biasing level of said clock means in response to a phase difference between said first and second signals to change the frequency of the pixel clock signals produced by said clock means.

Claim 11

Dependent Claim 45 words

The method according to claim 4 further characterized by: enabling a clock gate (70) with a start-of-scan signal; feeding back the signal output of said clock gate to said clock gate; and delaying said feedback by a preselected interval to control clock gate output frequency.

Pixel clock circuit and method of operating a raster imaging device

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