EP0048896A2
Expired / Lapsed
EP
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Clock synchronization signal generating circuit
Assignee: Toshiba Corp
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Filing: 1981-09-16
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Granted: —
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Expires: 2001-09-16
Abstract
Abstract A clock synchronization signal generating circuit includes a clock synchronizing circuit (12) having a scale variable counter (20) for counting a source clock signal from a source clock generator (10) and a control circuit (40) for controlling the scale of counter (20) responsive to the phase difference between an input clock signal supplied from a digital operation system and an output signal from the scale variable counter (20), and a clock circuit (14) including a counter for counting in n-scale mode a source clock signal from the source clock generator (10). The scale variable counter (20) is selectively set to (n-1)-, n- or (n + 1)-scale mode responsive to the control signal from the control circuit (40) to generate an output signal which is clock-synchronized with the input clock signal.
Inventors
- 👤 Haruki Yahata
- 👤 Hideo Suzuki
- 👤 Shunsuke Honda
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-24 11:45
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0331
Claims Analysis
Total Claims: 38
Claim 1
Independent Claim
226 words
A clock synchronization signal generating circuit comprising a source clock generating means (10), a clock synchronizing circuit (12, 52) connected to receive an input clock signal and a source clock signal from said source clock generating means (10) and generating an output signal which is clock-synchronized with the input clock signal, and a clock circuit (14, 54), characterized in that said clock synchronizing circuit (12, 52) includes first frequency dividing means (20, 24; 30, 34; 521, 523) for frequency-dividing the source clock signal from said source clock generating means (10) by a frequency dividing factor of N variable in a range of nl 2 N z n2 wherein nl, n2 and N are positive integers and nl > n2 and a control means (22, 32, 522) for controlling the frequency dividing factor of said first frequency dividing means to clock-synchronize an output signal from said first frequency dividing means with the input clock signal according to the phase relation between the input clock signal and the output signal from said first frequency dividing means, and that said clock circuit (14, 54) includes second frequency dividing means (40, 42; 541 to 543) for frequency-dividing the source clock signal from said source clock generating means (10) by a frequency dividing factor of n3 which is set to be substantially in a range of nl > n3 > n2.
Claim 2
Dependent Claim
226 words
A clock synchronization signal generating circuit comprising a source clock generating means (10), a clock synchronizing circuit (12, 52) connected to receive an input clock signal and a source clock signal from said source clock generating means (10) and generating an output signal which is clock-synchronized with the input clock signal, and a clock circuit (14, 54), characterized in that said clock synchronizing circuit (12, 52) includes first frequency dividing means (20, 24; 30, 34; 521, 523) for frequency-dividing the source clock signal from said source clock generating means (10) by a frequency dividing factor of N variable in a range of nl 2 N z n2 wherein nl, n2 and N are positive integers and nl > n2 and a control means (22, 32, 522) for controlling the frequency dividing factor of said first frequency dividing means to clock-synchronize an output signal from said first frequency dividing means with the input clock signal according to the phase relation between the input clock signal and the output signal from said first frequency dividing means, and that said clock circuit (14, 54) includes second frequency dividing means (40, 42; 541 to 543) for frequency-dividing the source clock signal from said source clock generating means (10) by a frequency dividing factor of n3 which is set to be substantially in a range of nl > n3 > n2.
Claim 3
Dependent Claim
22 words
A clock synchronization signal generating circuit according to claim 1 characterized in that nl is set to a value larger than (n2+l).
Claim 4
Dependent Claim
65 words
A clock synchronization signal generating circuit according to claim 1 or 2 characterized in that said first frequency dividing means includes a scale variable counting circuit (20, 521) for counting a source clock signal from said source clock generating means and whose scale N is controlled by said control means, and a decoding circuit (24, 522) for decoding an output signal from said counting circuit.
Claim 5
Dependent Claim
69 words
A clock synchronization signal generating circuit according to claim 3 characterized in that said second frequency dividing means includes an n4-scale counting circuit (40, 541) in which n4 is an integer in a range of nl > n4 > n2 and which counts a source clock signal from said source clock generating means (10), and a decoding circuit (42, 543) for decoding an output signal from said counting circuit.
Claim 6
Dependent Claim
75 words
A clock synchronization signal generating circuit according to claim 4 characterized in that said scale variable counting circuit (20, 521) generates a condition indicating signal when it comes to have a predetermined counting value in each of counting cycles and that said control means (22, 522) controls the scale of said scale variable counting circuit (20, 521) to be set according to the phase relation between said condition indicating signal and said input clock signal.
Claim 7
Dependent Claim
46 words
A clock synchronization signal generating circuit according to claim 4 characterized by further comprising an inhibit circuit (561 to 567) for inhibiting the output signal of said scale variable counting circuit (20, 521) when said scale variable counting circuit has contents different from predetermined counting contents.
Claim 8
Dependent Claim
75 words
A clock synchronization signal generating circuit according to claim 3 characterized in that said scale variable counting circuit (20, 521) generates a condition indicating signal when it comes to have a predetermined counting value in each of counting cycles and that said control means (22, 522) controls the scale of said scale variable counting circuit (20, 521) to be set according to the phase relation between said condition indicating signal and said input clock signal.
Claim 9
Dependent Claim
46 words
A clock synchronization signal generating circuit according to claim 3 characterized by further comprising an inhibit circuit (561 to 567) for inhibiting the output signal of said scale variable counting circuit (20, 521) when said scale variable counting circuit has contents different from predetermined counting contents.
Claim 10
Dependent Claim
40 words
A clock synchronization signal generating circuit according to claim 1 or 2 characterized in that said first frequency dividing means includes a first counting circuit (30) of n2-scale for counting a source clock signal from said source clock generating means
Claim 11
Dependent Claim
62 words
(10), a circuit (34) for preventing said source clock signal from being supplied to said first counting circuit (30) over an inhibition period defined by a control signal from said control signal from said control means (32) in each of counting cycles in said first counting circuit, and a decoding circuit for decoding an output signal from said first counting circuit (30).
Claim 12
Dependent Claim
62 words
(10), a circuit (34) for preventing said source clock signal from being supplied to said first counting circuit (30) over an inhibition period defined by a control signal from said control signal from said control means (32) in each of counting cycles in said first counting circuit, and a decoding circuit for decoding an output signal from said first counting circuit (30).
Claim 13
Dependent Claim
72 words
A clock synchronization signal generating circuit according to claim 9 characterized in that said second frequency dividing means includes a second counting circuit (40, 541) of n4-scale in which n4 is an integer in a range of nl > n4 > n2 and which counts a source clock signal from said source clock generating means (10), and a decoding circuit (42, 543) for decoding an output signal from said second counting circuit.
Claim 14
Dependent Claim
72 words
ll. A clock synchronization signal generating circuit according to claim 10 characterized in that said first counting circuit (30) generates a condition indicating signal when it comes to have a predetermined counting value in each of counting cycles, and that said control means (32) sets the length of said inhibition period of time to a predetermined value according to the phase relation between said condition indicating signal and said input clock signal.
Claim 15
Dependent Claim
19 words
A clock synchronization signal generating circuit according to claim 1 characterized in that nl is set equal to (n2+l).
Claim 16
Dependent Claim
66 words
A clock synchronization signal generating circuit according to claim 12 characterized in that said second frequency dividing means includes a first scale variable counting circuit (541, 542) for operating as n3-scale counter to count selectively in nl- or n2-scale mode a source clock signal from said source clock generating means (10), and a decoding circuit (543) for decoding an output signal of said first counting circuit.
Claim 17
Dependent Claim
66 words
A clock synchronization signal generating circuit according to claim 13 characterized in that said first frequency dividing means includes a second scale variable counting circuit (20, 521) for counting a source clock signal applied from said source clock generating means and whose scale N is controlled by said control means, and a decoding circuit (24, 522) for decoding an output signal from said second counting circuit.
Claim 18
Dependent Claim
77 words
A clock synchronization signal generating circuit according to claim 14 characterized in that said second scale variable counting circuit (20, 521) generates a condition indicating signal when it comes to have a predetermined counting value in each of counting cycles and that said control means (22, 522) controls the scale of said second scale variable counting circuit (20, 521) to be set according to the phase relation between said condition indicating signal and said input clock signal.
Claim 19
Dependent Claim
47 words
A clock synchronization signal generating circuit according to claim 14 characterized by further comprising a circuit (561 to 567) for preventing the output signal of said second scale variable counting circuit (20, 521) when said second scale variable counting circuit has contents different from predetermined counting contents.
Claim 20
Dependent Claim
69 words
A clock synchronization signal generating circuit according to claim 1 characterized in that said second frequency dividing means includes a first scale variable counting circuit (541, 542) for operating substantially as n3-scale counter circuits to count selectively in at least two different scales a source clock signal from said source clock generating means (10), and a decoding circuit (543) for decoding an output signal of said first counting circuits.
Claim 21
Dependent Claim
65 words
A clock synchronization signal generating circuit according to claim 17 characterized in that said first frequency dividing means includes a second scale variable counting circuit (20, 521) for counting a source clock signal from said source clock generating means and whose scale N is controlled by said control means, and a decoding circuit (24, 522) for decoding an output signal from said second counting circuit.
Claim 22
Dependent Claim
77 words
A clock synchronization signal generating circuit according to claim 18 characterized in that said second scale variable counting circuit (20, 521) generates a condition indicating signal when it comes to have a predetermined counting value in each of counting cycles and that said control means (22, 522) controls the scale of said second scale variable counting circuit (20, 521) to be set according to the phase relation between said condition indicating signal and said input clock signal.
Claim 23
Dependent Claim
47 words
A clock synchronization signal generating circuit according to claim 18 characterized by further comprising a circuit (561 to 567) for preventing an output signal of said second scale variable counting circuit (20, 521) when said second scale variable counting circuit has contents different from predetermined counting contents.
Claim 24
Dependent Claim
168 words
A clock synchronization signal generating circuit characterized by variable frequency dividing means (20, 24; 30, 34; 521, 523) for frequency-dividing a source clock signal from a source clock generating means (10) by a frequency dividing factor N variable in a range of nl a N Z n2 wherein nl, n2 and N are positive integers and nl > n2, and control means (18, 23) for supplying a first control signal to said frequency dividing means in first operation mode to set the frequency dividing factor of said variable frequency dividing means to a value of n3 larger than n2 but smaller than nl and for supplying a second control signal to said variable frequency dividing means in second operation mode according to the phase relation between an input clock signal and an output signal from said variable frequency dividing means to control the frequency dividing factor of said variable frequency dividing means to clock-synchronize the output signal of said variable frequency dividing means with the input clock signal.
Claim 25
Dependent Claim
168 words
A clock synchronization signal generating circuit characterized by variable frequency dividing means (20, 24; 30, 34; 521, 523) for frequency-dividing a source clock signal from a source clock generating means (10) by a frequency dividing factor N variable in a range of nl a N Z n2 wherein nl, n2 and N are positive integers and nl > n2, and control means (18, 23) for supplying a first control signal to said frequency dividing means in first operation mode to set the frequency dividing factor of said variable frequency dividing means to a value of n3 larger than n2 but smaller than nl and for supplying a second control signal to said variable frequency dividing means in second operation mode according to the phase relation between an input clock signal and an output signal from said variable frequency dividing means to control the frequency dividing factor of said variable frequency dividing means to clock-synchronize the output signal of said variable frequency dividing means with the input clock signal.
Claim 26
Dependent Claim
22 words
A clock synchronization signal generating circuit according to claim 21 characterized in that nl is set to a value larger than (n2+l).
Claim 27
Dependent Claim
62 words
A clock synchronization signal generating circuit according to claim 21 or 22 characterized in that said variable frequency dividing means includes a scale variable counting circuit (20, 30, 521) whose scale N is controlled responsive to the second control signal from said control means (18, 23), and a decoding circuit (24, 34, 523) for decoding an output signal from said counting circuit.
Claim 28
Dependent Claim
78 words
A clock synchronization signal generating circuit according to claim 23 characterized in that said scale variable counting circuit (20, 521) generates a condition indicating signal when it comes to have a predetermined counting value in each of counting cycles, and said control means (22, 522) controls the scale of said scale variable counting circuit (20, 521) in second operation mode to be set according to the phase relation between said condition indication signal and said input clock signal.
Claim 29
Dependent Claim
45 words
A clock synchronization signal generating circuit according to claim 23 characterized by further comprising a circuit (561 to 567) for inhibiting the output signal of said scale variable counting circuit when said scale variable counting circuit (20, 521) has contents different from predetermined counting contents.
Claim 30
Dependent Claim
95 words
A clock synchronization signal generating circuit according to claim 21 or 22 characterized in that said variable frequency dividing means includes a scale variable counting circuit (20, 521) for carrying out n4-scale counting operation responsive to the first control signal from said control means (18, 23) in which n4 is an integer in a range of nl > n4 > n2 and whose scale N is controlled responsive to the second control signal from said control means (18, 23), and a decoding circuit (24, 34, 523) for decoding an output signal from said counting circuit.
Claim 31
Dependent Claim
78 words
A clock synchronization signal generating circuit according to claim 26 characterized in that said scale variable counting circuit (20, 521) generates a condition indicating signal when it comes to have a predetermined counting value in each of counting cycles, and said control means (22, 522) controls the scale of said scale variable counting circuit (20, 521) in second operation mode to be set according to the phase relation between said condition indicating signal and said input clock signal.
Claim 32
Dependent Claim
45 words
A clock synchronization signal generating circuit according to claim 26 characterized by further comprising a circuit (561 to 567) for inhibiting the output signal of said scale variable counting circuit when said scale variable counting circuit (20, 521) has contents different from predetermined counting contents.
Claim 33
Dependent Claim
110 words
A clock synchronization signal generating circuit according to claim 21 or 22 characterized in that said variable frequency dividing means includes a counting circuit (30 of n2-scale for counting a source clock signal from said source clock generating means (10), a clock preventing circuit (34) for preventing the source clock signal over a first preventing period defined by the first control signal supplied from said control means (18, 23) and over a second preventing period selectively defined by the second control signal supplied from said control means in each of counting cycles in said counting circuit (30), and a decoding circuit for decoding an output signal from said counting circuit.
Claim 34
Dependent Claim
72 words
A clock synchronization signal generating circuit according to claim 29 characterized in that said first counting circuit (30) generates a condition indicating signal when it comes to have a predetermined counting value in each of counting cycles, and said control means (32) sets in second operation mode the length of said preventing period to a predetermined value according to the phase relation between said condition indicating signal and said input clock signal.
Claim 35
Dependent Claim
74 words
A clock synchronization signal generating circuit according to claim 21 characterized in that said variable frequency dividing means includes a scale variable counting circuit for selectively counting with at least two different scales, responsive to the first control signal from said control means (18, 23), a source clock signal from said source clock generating means (10) to carry out n3-scale counting operation, and a decoding circuit for decoding an-output signal from said counting circuit.
Claim 36
Dependent Claim
45 words
A clock synchronization signal generating circuit according to claim 31 characterized in that said scale variable counting circuit counts a source clock signal from said source clock generating means (10) in a scale N controlled responsive to the second control signal from said control means.
Claim 37
Dependent Claim
78 words
A clock synchronization signal generating circuit according to claim 32 characterized in that said scale variable counting circuit (20, 521) generates a condition indicating signal when it comes to have a predetermined counting value in each of counting cycles, and said control means (22, 522) controls the scale of said scale variable counting circuit (20, 521) in second operation mode to be set according to the phase relation between said condition indicating signal and said input clock signal.
Claim 38
Dependent Claim
45 words
A clock synchronization signal generating circuit according to claim 32 characterized by further comprising a circuit (561 to 567) for preventing the output signal of said scale variable counting circuit when said scale variable counting circuit (20, 521) has contents different from predetermined counting contents.
References Cited (Backward Citations)
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