Pulse code modulation signal recording and reproducing

Claim 2

A PCM signal recording system comprising first signal processing means (1 to 7) for processing a recording signal into a predetermined PCM signal, second signal processing means (18 to 24) for processing a reproduced PCM signal into said recording signal, first clock signal generating means (9) for generating a master clock signal, second clock signal generating means (12 to 14) for generating at least one recording clock signal from said master clock signal, said recording clock signal being supplied to said first signal processing means (1 to 7), and third clock signal generating means (27) for generating at least one reproducing clock signal related to said master clock signal, said reproducing clock signal being supplied to said second signal processing means (18 to 24), characterised by comparing means (32) for digitally comparing the phases of said second clock signal and said third clock signal and for producing a control signal, and control means (29) for controlling said second and third clock signals in dependence on said control signal so that they are synchronized with each other.

Claim 3

A PCM signal recording system according to claim 1 wherein said control means (29) is provided in said third clock signal generating means (27).

Claim 4

A PCM signal recording system according to claim 2 wherein said third clock signal generating means (27) includes a programmable divider (29) for dividing said master clock signal and the dividing ratio can be increased or decreased by the control signal.

Claim 5

A PCM signal recording system according to claim 1 further comprising detecting means (44) for detecting whether said second or said third clock signal is supplied to said comparing means (32) and connected for controlling said comparing means (32) so that it is operative only when said second or said third clock signal is supplied to said comparing means (32).

Claim 6

A PCM signal recording and reproducing circuit comprising a recording circuit (7), a master oscillator (9), first frequency dividing means (12 to 14) for supplying an output to said recording circuit (7), first switch means (10) for selectively connecting the output of said master oscillator (9) to said first frequency dividing means (12 to 14), a reproducing circuit (21) arranged to receive a reproduced video signal and process it, a variable frequency oscillator (27) for supplying an input to said reproducing circuit (21), a data separation circuit (20) for receiving said reproduced video signal and supplying an input to said reproducing circuit (21), second controllable frequency dividing means (28 to 31) for receiving an output of said frequency variable oscillator (27) and supplying an input to said reproduced circuit (21), characterised by a first comparator means (25) for receiving inputs from said data separation circuit (20) and said second controllable frequency dividing means (28 to 31) and supplying an input to said variable frequency oscillator (27) to control its output frequency, the output of said variable frequency oscillator (27) being supplied through said first switch means (10) to said first frequency dividing means (12 to 14), and a second comparator means (32) for receiving inputs from said first dividing means (12 to 14) and said second controllable frequency dividing means (28 to 31) and supplying an input to said second controllable frequency dividing means (28 to 31) to control its dividing ratio.

Claim 7

A PCM signal recording and reproducing circuit comprising a recording circuit (7), a master oscillator (9), first frequency dividing means (12 to 14) for supplying an output to said recording circuit (7), first switch means (10) for selectively connecting the output of said master oscillator (9) to said first frequency dividing means (12 to 14), a reproducing circuit (21) arranged to receive a reproduced video signal and process it, a variable frequency oscillator (27) for supplying an input to said reproducing circuit (21), a data separation circuit (20) for receiving said reproduced video signal and supplying an input to said reproducing circuit (21), second controllable frequency dividing means (28 to 31) for receiving an output of said frequency variable oscillator (27) and supplying an input to said reproduced circuit (21), characterised by a first comparator means (25) for receiving inputs from said data separation circuit (20) and said second controllable frequency dividing means (28 to 31) and supplying an input to said variable frequency oscillator (27) to control its output frequency, the output of said variable frequency oscillator (27) being supplied through said first switch means (10) to said first frequency dividing means (12 to 14), and a second comparator means (32) for receiving inputs from said first dividing means (12 to 14) and said second controllable frequency dividing means (28 to 31) and supplying an input to said second controllable frequency dividing means (28 to 31) to control its dividing ratio.

Claim 8

A PCM signal recording and reproducing circuit according to claim 5 wherein said frequency variable oscillator (27) is a voltage controlled oscillator (27).

Claim 9

A PCM signal recording and reproducing circuit according to claim 6 including a low-pass filter (26) connected between said first comparator means (25) and said voltage controlled oscillator (27).

Claim 10

A PCM recording and reproducing circuit according to claim 5 wherein said first frequency dividing means (12 to 14) includes a plurality of dividing stages.

Claim 11

A PCM recording and reproducing circuit according to claim 5 wherein said second controllable frequency dividing means (28 to 31) includes at least one dividing stage (28, 30, 31) which has a fixed dividing ratio and at least one dividing stage (29) which has a controllable dividing ratio.

Claim 12

A PCM recording and reproducing circuit according to claim 9 wherein said one dividing stage (28, 30, 31) which has a fixed dividing ratio is a digital counter (28, 30, 31).

Claim 13

A PCM recording and reproducing circuit according to claim 9 wherein said dividing stage (29) with a controllable dividing ratio is a digital counter (29).

Claim 14

A PCM circuit according to claim 11 including at least two digital control terminals on said digital counter (29) which has a controllable dividing ratio and said second comparator means (32) produces at least two digital output signals which are connected to said two digital control terminals.

Claim 15

A PCM circuit according to claim 12 wherein said second comparator means (32) comprises at least two flip-flop circuits (35, 36).

Claim 16

A PCM circuit according to claim 13 wherein a second switch means (45) is connected to one of said two flip-flop circuits (35, 36).

Claim 17

A PCM circuit according to claim 13 including a triggerable monostable circuit (44) connected to one of said two flip-flop circuits (35).

Claim 18

A PCM circuit according to claim 13 including a third flip-flop circuit (41) in said second comparator means (32).