EP0054102A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Very high density cells comprising a ROM and method of manufacturing same
Assignee: Boeing North American Inc
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Filing: 1981-08-28
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Granted: —
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Expires: 2001-08-28
Abstract
Abstract The subject invention conserves memory real estate by employing ROM cells which are FETs or non-FETs depending upon the programming. Each cell comprises a gate, a source and drain region and provision for connections to bit and word lines. Programming is achieved by a mask which permits doping of the source and drain regions to comprise FETs for the cells indicative of one state of logic while precluding doping of the source and drain regions to complete the channel in the cells comprising the other state of logic. Also, the FETs are fabricated, their contacts extending linearly between bit lines which are preferably diffused lines, and the word line making direct contact with gates of the linear cells. The process simplifies the number of steps required to manufacture the FETs and non-FETs by simply providing the programming after the basic cells are formed. Such unprogrammed structures may be inventoried and simply programmed i.e. completed by selective doping and establishing of contacts to fulfill orders to customer specifications immediately.
Inventors
- 👤 Frank Zuchov Custode
- 👤 Matthias Lapkay Tam
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 10:27
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10B; H10B20/00; H10B20/27; H10B20/30; H10B20/34; H10B20/38; H10B20/387; H10W; H10W20/00; H10W20/20
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
67 words
A high speed ROM comprising, in combination: a plurality of cells, each comprising at least a source, drain and gate; means for establishing electrical connections and each source, drain and gate; certain of said cells having a channel between the source and drain to provide an indication of one logic state; and, others of said cells having no channel to provide an indication of another logic state.
Claim 2
Dependent Claim
67 words
A high speed ROM comprising, in combination: a plurality of cells, each comprising at least a source, drain and gate; means for establishing electrical connections and each source, drain and gate; certain of said cells having a channel between the source and drain to provide an indication of one logic state; and, others of said cells having no channel to provide an indication of another logic state.
Claim 3
Dependent Claim
31 words
The ROM of Claim 1, wherein: said means comprises word and bit lines; and, said word lines extending substantially directly over the gates of groups of cells making electrical contact therewith.
Claim 4
Dependent Claim
20 words
The ROM of Claim 2, wherein: said cells have their sources, gates and drains in linear alignment between bit lines.
Claim 5
Dependent Claim
29 words
The ROM of Claim 3, wherein: programming is effected by virtue of a mask which precludes doping of the channel regions of said other cells thereby precluding channel formation.
Claim 6
Dependent Claim
97 words
A VLSI high density incomplete ROM formed on a substrate by process steps comprising, in combination: a plurality of cells; field oxide surrounding each cell; a source region, gate region and drain region for each cell; and, means predetermining which cells are to be completed by doping the source and drain regions to extend to the gate region to comprise FETS to program the ROM whereby said incomplete ROMs may be inventoried until said program is ascertained, and then completed by said means, a doping step, and a step establishing interconnects to said source, gate, and drain.
Claim 7
Dependent Claim
97 words
A VLSI high density incomplete ROM formed on a substrate by process steps comprising, in combination: a plurality of cells; field oxide surrounding each cell; a source region, gate region and drain region for each cell; and, means predetermining which cells are to be completed by doping the source and drain regions to extend to the gate region to comprise FETS to program the ROM whereby said incomplete ROMs may be inventoried until said program is ascertained, and then completed by said means, a doping step, and a step establishing interconnects to said source, gate, and drain.
Claim 8
Dependent Claim
120 words
A process for manufacturing high density VLSI ROMs comprising cells which are FETS or incomplete FETS to determine the ROM programing comprising the steps of: forming gate dielectrics on a substrate each comprising silicon oxide covered by polysilicon; surrounding each cell by field oxide; doping regions on opposite sides of the gates and spaced therefrom to provide n+ diffused bit lines; providing word lines in contact with the polysilicon of ions of gates of said cells; and, doping source and drain regions of selected cells from said n+ diffused,lines respectively to the associated gate to form FETS to provide an indication of a logic state different from a logic state determinable from ROM-FET cells having undoped source and drain regions.
Claim 9
Dependent Claim
120 words
A process for manufacturing high density VLSI ROMs comprising cells which are FETS or incomplete FETS to determine the ROM programing comprising the steps of: forming gate dielectrics on a substrate each comprising silicon oxide covered by polysilicon; surrounding each cell by field oxide; doping regions on opposite sides of the gates and spaced therefrom to provide n+ diffused bit lines; providing word lines in contact with the polysilicon of ions of gates of said cells; and, doping source and drain regions of selected cells from said n+ diffused,lines respectively to the associated gate to form FETS to provide an indication of a logic state different from a logic state determinable from ROM-FET cells having undoped source and drain regions.
Claim 10
Dependent Claim
26 words
The process of Claim 6 further comprising: forming gating transistors on said substrate; and, interconnecting gates from at least certain FETS to sources of said transistors.
Claim 11
Dependent Claim
24 words
The process of Claim 7, further comprising: doping the regions of said substrate beneath the field oxide to better isolate the cells and transistors.
Claim 12
Dependent Claim
32 words
The process of Claim 8, wherein: the selection of cells to comprise FETS is determined by a preprogrammed mask which precludes doping of the source and drain regions of the non-selected cells.
Claim 13
Dependent Claim
52 words
The process of Claim 9, wherein: contacts are established to the gates of said FETS, non-FETS and transistors by protecting the gate polysilicon from other process steps through the provision of a silicon nitride button thereover, and the selective removal of said buttons by etching simultaneously just prior to a metallization step.
References Cited (Backward Citations)
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