Method of manufacturing a semiconductor device of the mis type

Claim 1

A method for manufacturing a semiconductor device comprising the steps of (a) forming a gate insulating film (3, 23, 33, 43, 53, 63) on a surface of a silicon substrate (1, 21, 31, 41, 51, 61), and a gate electrode (4, 24, 34, 44, 54, 64) on said gate insulating film (3, 23, 33, 43, 53, 63); (b) forming an insulating film (6, 26a, 26b, 36, 45, 55, 65) on the surface of said silicon substrate (1, 21, 31, 41, 51, 61) and said gate electrode (4, 24, 34, 44, 54, 64), (c) forming a metal or metal silicide film (9, 29, 39, 49, 57a, 57b, 57c, 67a, 67b, 67c) on a region including a source region (5a, 25a, 35a, 48a, 58a, 68a), a drain region (5b, 25b, 35b, 48b, 58b, 68b) and a diffusion interconnection region (5c, 25c, 35c, 48c) which is an extended part of at least one of said source region and said drain region, or prospective regions for said source, drain and diffusion interconnection regions; and (d) forming said source region, said drain region and said diffusion interconnection region which is the extended part of at least one of said source region and said drain region, by doping at least once said substrate with an impurity which has a conductivity type opposite to a conductivity type of said silicon substrate any time after step (a), characterized in that step (b) includes etching said insulating film (6, 26a, 26b, 36, 45, 55, 65) by anisotropic etching thus leaving a self-aligned insulating film (6, 26a, 38, 46, 55, 65) on the side walls of said gate electrode (4, 24, 34, 44, 54, 64) and removing the insulating film from the source, drain and the diffusion interconnection regions to expose the same, and said metal or metal silicide film is formed in a self-aligned manner only on the source, drain and diffusion interconnections regions from which the insulating film is removed by the anisotropic etching.

Claim 2

A method for manufacturing a semiconductor device comprising the steps of (a) forming a gate insulating film (3, 23, 33, 43, 53, 63) on a surface of a silicon substrate (1, 21, 31, 41, 51, 61), and a gate electrode (4, 24, 34, 44, 54, 64) on said gate insulating film (3, 23, 33, 43, 53, 63); (b) forming an insulating film (6, 26a, 26b, 36, 45, 55, 65) on the surface of said silicon substrate (1, 21, 31, 41, 51, 61) and said gate electrode (4, 24, 34, 44, 54, 64), (c) forming a metal or metal silicide film (9, 29, 39, 49, 57a, 57b, 57c, 67a, 67b, 67c) on a region including a source region (5a, 25a, 35a, 48a, 58a, 68a), a drain region (5b, 25b, 35b, 48b, 58b, 68b) and a diffusion interconnection region (5c, 25c, 35c, 48c) which is an extended part of at least one of said source region and said drain region, or prospective regions for said source, drain and diffusion interconnection regions; and (d) forming said source region, said drain region and said diffusion interconnection region which is the extended part of at least one of said source region and said drain region, by doping at least once said substrate with an impurity which has a conductivity type opposite to a conductivity type of said silicon substrate any time after step (a), characterized in that step (b) includes etching said insulating film (6, 26a, 26b, 36, 45, 55, 65) by anisotropic etching thus leaving a self-aligned insulating film (6, 26a, 38, 46, 55, 65) on the side walls of said gate electrode (4, 24, 34, 44, 54, 64) and removing the insulating film from the source, drain and the diffusion interconnection regions to expose the same, and said metal or metal silicide film is formed in a self-aligned manner only on the source, drain and diffusion interconnections regions from which the insulating film is removed by the anisotropic etching.

Claim 6

A method according to any one of claims 1 to 4, characterized in that step (d) is performed between steps (a) and (b), and annealing is performed after step (d).

Claim 7

A method according to any one of claims 1 to 4, characterized in that step (d) is performed between steps (a) and (b) and between steps (b) and (c), dose of the impurity in doping between steps (b) and (c) being higher than that in doping between steps (a) and (b), and that annealing is performed at least one time after step (d).