Semiconductor device for memory cell

Claim 2

A semiconductor device for a memory cell for a read only memory, said semiconductor device comprising a semiconductor substrate, an insulator layer on said semiconductor substrate, and a semiconductor layer on said insulator layer and being adapted to provide the memory cell with characteristics corresponding to "1" or "0" information to be stored; said correspondence to "1" or "0" information being achieved by changing the conductivity type of at least a portion of said semiconductor layer in said semiconductor device.

Claim 3

A semiconductor device having a metal insulator semiconductor type transistor for forming a memory cell for a read only memory, said semiconductor device comprising a semiconductor substrate, an insulator layer on said semiconductor substrate, and a semiconductor layer on said insulator layer and being adapted to provide the memory cell with characteristics corresponding to "l" or "0" information to be stored; said correspondence to "1" or "0" information being achieved by changing the conductivity type of at least a portion of said semiconductor layer in said semiconductor device.

Claim 4

A semiconductor device having a metal insulator semiconductor type transistor for forming a memory cell for a read only memory, said semiconductor device comprising a semiconductor substrate, an insulator layer on said semiconductor substrate, and a semiconductor layer on said insulator layer and being adapted to provide the memory cell with characteristics corresponding to "l" or "0" information to be stored; said correspondence to "1" or "0" information being achieved by changing the conductivity type of at least a portion of said semiconductor layer in said semiconductor device.

Claim 5

A semiconductor device for a memory cell for a read only memory having a plurality of X-axis lines, a plurality of Y-axis lines, and a plurality of memory cells located at the intersections of said X- and Y-axis lines, said X-axis lines being formed by conductor layers arranged on a semiconductor layer on an insulator layer on a semiconductor substrate, said Y-axis lines being formed by impurity regions in said semiconductor substrate, said semiconductor device comprising a semiconductor substrate, an insulator layer on said semiconductor substrate, and a semiconductor layer on said insulator layer and being adapted to become a having characteristics corresponding to "1" or "0" information to be stored, said correspondence to "1" or "0" information being achieved by changing the conductivity type of at least a portion of said semiconductor layer in said semiconductor device.

Claim 6

A semiconductor device for a memory cell for a read only memory having a plurality of X-axis lines, a plurality of Y-axis lines, and a plurality of memory cells located at the intersections of said X- and Y-axis lines, said X-axis lines being formed by conductor layers arranged on a semiconductor layer on an insulator layer on a semiconductor substrate, said Y-axis lines being formed by impurity regions in said semiconductor substrate, said semiconductor device comprising a semiconductor substrate, an insulator layer on said semiconductor substrate, and a semiconductor layer on said insulator layer and being adapted to become a having characteristics corresponding to "1" or "0" information to be stored, said correspondence to "1" or "0" information being achieved by changing the conductivity type of at least a portion of said semiconductor layer in said semiconductor device.

Claim 7

A read-only semiconductor memory cell structure, comprising a semiconductor substrate with source, channel and drain regions of a MIS FET formed therein, an insulator layer on the semiconductor substrate over the said regions, and a semiconductor layer, providing a gate of the MIS FET, on the insulator layer, the semiconductor layer having first and second portions of respective different conductivity types, a selected one of those portions, selected in accordance with the data value, "1" or "0", to be held in the memory cell structure, extending over the channel region of the MIS FET.

Claim 8

A read-only semiconductor memory cell structure, comprising a semiconductor substrate with source, channel and drain regions of a MIS FET formed therein, an insulator layer on the semiconductor substrate over the said regions, and a semiconductor layer, providing a gate of the MIS FET, on the insulator layer, the semiconductor layer having first and second portions of respective different conductivity types, a selected one of those portions, selected in accordance with the data value, "1" or "0", to be held in the memory cell structure, extending over the channel region of the MIS FET.

Claim 9

A structure as claimed in claim 4, in respect of which the data value to be held in the completed cell structure requires the second portion to extend over the channel region and in the course of manufacture of which the first portion of the semiconductor layer was provided to extend over the channel region, wherein the extension of the second portion over the channel region is provided by ion implanted impurities, ion implantation of impurities of appropriate conductivity type and in appropriate quantity having been effected to change the conductivity type of that part of the semiconductor layer over the channel region to the conductivity type of the said second portion.

Claim 10

A read only memory comprising an array of memory cell structures as claimed in claim 4.

Claim 11

A logic array comprising an array of memory cell structures as claimed in claim 4.