EP0072219A2
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Memory addressing system
Assignee: Toshiba Corp
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Filing: 1982-08-05
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Granted: —
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Expires: 2002-08-05
Abstract
Abstract Addressing systems are described which enable the size of the addressable memory space to be increased. A first memory from which data is normally read and a second memory into which data is normally written are assigned to the same address space. In a first mode of operation the first memory can be selected by a read a signal and the second memory by a write signal. In a second mode of operation the first and second memories are selected by write and read signals respectively. Arrangements are described where the first memory is ROM and the second memory RAM and in the second mode of operation the RAM is accessed for both reading and writing. The arrangements of the memories in the addressable memory space is alterable.
Inventors
- 👤 Ishii C/O Patent Division Takatoshi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 05:23
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0615; G06F12/0623
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
65 words
A memory addressing system comprising: a first memory; a second memory; means for addressing the first and second memories, each address corresponding to one memory location in both the first and second memories; and means for selecting one of the first and second memories when data is to be read and the other of the first and second memories when data is to be written.
Claim 2
Dependent Claim
65 words
A memory addressing system comprising: a first memory; a second memory; means for addressing the first and second memories, each address corresponding to one memory location in both the first and second memories; and means for selecting one of the first and second memories when data is to be read and the other of the first and second memories when data is to be written.
Claim 3
Dependent Claim
94 words
A memory addressing system as claimed in claim 1, wherein: the first and second memories are both read/write memories; said selecting means including means for selecting: the first memory when data is to be read and the second memory when data is to be written during a first mode of operation, and the first memory when data is to be written and the second memory when data is to be read during a second mode of operation; and- the system including means for instituting either one of said first and second modes of operation.
Claim 4
Dependent Claim
86 words
A memory addressing system as claimed in claim 1 wherein: the second memory is a read/write memory; and the selecting means including means for selecting: the first memory when data is to be read and the second memory when data is to be written during a first mode of operation, and the second memory when data is to be either read or written during a second mode of operation; and the system including means for instituting either one of the first and second modes of operation.
Claim 5
Dependent Claim
135 words
A memory addressing system as claimed in claim 1 wherein: the system further comprises a third memory; the selecting means includes means for selecting: the third memory in response to a third memory address signal, one of the first and second memories in response to both a first and second memory address signal and a read signal, and the other of said first and second memories in response to both the first and second memory address signal and a write signal during a first mode of operation; and the first memory in response to the first and second memory address signal, and the second memory in response to the third memory address signal during,a second mode of operation; and the system including means for instituting either one of the first and second modes of operation.
Claim 6
Dependent Claim
122 words
A memory addressing system as claimed in claim 1 wherein: the system further comprises a third memory; the selecting means including means for selecting one of the first and second memories in response to a first and second memory address signal and a read signal, the other of the first and second memories in response to both the first and second memory address signal and a write signal, and for selecting the third memory in response to a third memory address signal, during a first mode of operation; and the second memory in response to said third memory address signal secod mode of operation; and the system further comprises means for instituting either one of said first and second modes of operation.
Claim 7
Dependent Claim
141 words
A memory addressing system as claimed in claim 1 wherein: the second memory is a read/write memory; the system further comprises a third memory; the selecting means including means for selecting the first memory in response to a first and second memory address signal and a read signal, and said second memory in response to the first and second memory address signal and a write signal; and for selecting the third memory in response to a third memory address signal during a first mode of operation, and the third memory in response to the third memory address signal and a write signal, and the second memory in response to the third memory address signal and a read signal in a second mode of operation; and the system including means for instituting either one of said first and second modes of operation.
Claim 8
Dependent Claim
20 words
A memory addressing system as claimed in claim 1, 4 or 5 wherein the second memory is a read/write memory.
Claim 9
Dependent Claim
18 words
A memory addressing system as claimed in claim 7, wherein said second memory comprises a CRT refresh memory.
Claim 10
Dependent Claim
78 words
A memory addressing system as claimed in claim 2, 3, 4 or 6, wherein the means for selecting and means for instituting comprises: decoding means for selecting the first and second memories; a flip-flop for generating a mode setting signal representing a selected mode of operation; and selecting means, responsive to the flip.flop and the decoding means, for selecting either one of the first and second memories in response to the mode setting signal and a read/write signal.
Claim 11
Dependent Claim
20 words
A memory addressing system as claimed in claim 4, 5 or 6, wherein the third memory is a read/write memory.
Claim 12
Dependent Claim
20 words
A memory addressing system as claimed in claim 4, 5 or 6, wherein the third memory is a read/write memory.
References Cited (Backward Citations)
No citation records indexed.
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