EP0073608A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Masterslice integrated circuit device and method for manufacturing the same
Assignee: Fujitsu Ltd
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Filing: 1982-08-18
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Granted: —
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Expires: 2002-08-18
Abstract
Abstract in a masterslice integrated circuit, a plurality of input and output logic gates and a plurality of internal logic gates are arranged in the form of an array. A custom-made wiring pattern is arranged between the input and output logic gates and the internal logic gates. At least one of the logic gates comprises a plurality of PNP transistors (Q 11 ∞ Q 15 ) and a plurality of output stage circuits (OS A , OS B ). In addition, by the custom-made wiring pattern, one of the output stage circuits is connected to the emitter of at least one of the PNP transistors to form one of the logic gates.
Inventors
- 👤 Hitoshi Omichi
- 👤 Tetsu Tanizawa
- 👤 Yoshiharu Mitono
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 10:23
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/901; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/088; H03K19/173; H03K19/1733; H03K19/1735
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
169 words
A masterslice integrated circuit device including a plurality of input and output logic gates disposed in a peripheral region thereof, a plurality of internal logic gates disposed in a central region thereof, and a desired wiring pattern connectinoesaid logic gates to provide desired circuit functions, said logic gates being arranged in the form of an array, at least one of said logic gates comprising: a plurality of PNP transistors (Q 11 ~ Q15), each of said PNP transistors having a base for receiving a first signal and an emitter for providing a second signal corresponding to said first signal; and a plurality of output stage circuits (OS A , OS B ) which are arranged at positions so that at least one of said PNP transistors can be connected to one of said output stage circuits by said desired wiring pattern, one of said output stage circuits being connected to the emitter of at least one of said plurality of PNP transistors to form one of said logic gates.
Claim 2
Dependent Claim
169 words
A masterslice integrated circuit device including a plurality of input and output logic gates disposed in a peripheral region thereof, a plurality of internal logic gates disposed in a central region thereof, and a desired wiring pattern connectinoesaid logic gates to provide desired circuit functions, said logic gates being arranged in the form of an array, at least one of said logic gates comprising: a plurality of PNP transistors (Q 11 ~ Q15), each of said PNP transistors having a base for receiving a first signal and an emitter for providing a second signal corresponding to said first signal; and a plurality of output stage circuits (OS A , OS B ) which are arranged at positions so that at least one of said PNP transistors can be connected to one of said output stage circuits by said desired wiring pattern, one of said output stage circuits being connected to the emitter of at least one of said plurality of PNP transistors to form one of said logic gates.
Claim 3
Dependent Claim
137 words
A device as set forth in claim 1, wherein each of said output stage circuits includes: first and second power supply terminals (GND, VCC); a first NPN transistor (Q 2 ) having a base connected to the emitter of at least one of said plurality of PNP transistors, a collector connected to said second power supply terminal; and an emitter; a second NPN transistor (Q 3 ) having a base connected to the collector of said first NPN transitor, a collector connected to said second power supply terminal, and an emitter; and a third NPN transistor (Q 4 ) having a base connected to the emitter of said first NPN transistor, a collector connected to the emitter of said second NPN transistor and serving as one output, and an emitter connected to said first power supply terminal.
Claim 4
Dependent Claim
46 words
A device as set forth in claim 2, wherein each of said output stage circuits further includes a diode (D 1 ) having an anode connected to the emitter of said second NPN transistor and a cathode connected to the collector of said second NPN transistor.
Claim 5
Independent Claim
186 words
A method for manufacturing a masterslice integrated circuit device including a plurality of input and output logic gates disposed in a peripheral region thereof, a plurality of internal logic gates disposed in a central region thereof, and a -desired wiring pattern disposed between said logic gates to provide desired circuit functions, said logic gates being arranged in the form of an array, said method comprising the steps of: forming a plurality of PNP transistors, each of said PNP transistors having a base for receiving a first signal and an emitter for providing a second signal corre- sponding to said first signal; forming a plurality of output stage circuits at positions so that at least one of said - PNP transistors can be connected to one of said output stage circuits, each of said plurality of output stage circuits having an input and an output terminals; and electrically connecting the emitter of at least one of said plurality of PNP transistors to the input terminal of one of said plurality of output stage circuits to form one of said logic gates, using the said desired wiring pattern.
Claim 6
Independent Claim
186 words
A method for manufacturing a masterslice integrated circuit device including a plurality of input and output logic gates disposed in a peripheral region thereof, a plurality of internal logic gates disposed in a central region thereof, and a -desired wiring pattern disposed between said logic gates to provide desired circuit functions, said logic gates being arranged in the form of an array, said method comprising the steps of: forming a plurality of PNP transistors, each of said PNP transistors having a base for receiving a first signal and an emitter for providing a second signal corre- sponding to said first signal; forming a plurality of output stage circuits at positions so that at least one of said - PNP transistors can be connected to one of said output stage circuits, each of said plurality of output stage circuits having an input and an output terminals; and electrically connecting the emitter of at least one of said plurality of PNP transistors to the input terminal of one of said plurality of output stage circuits to form one of said logic gates, using the said desired wiring pattern.
References Cited (Backward Citations)
No citation records indexed.
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