Memory control circuit for subsystem controller

Claim 2

In a processor-controller for a data communications network wherein said processor-controller executes data transfers between a main host computer and a plurality of line communication processors connected to remote data terminals via line adapters, and wherein said processor-controller provides a master processor, for controlling data transfers to/from said host computer, and provides a slave processor, for controlling data transfers to said line communication processors, a memory control circuit comprising: (a) a master memory control unit, connected to said master processor, for servicing memory requests of said master processor; (b) a slave memory control unit, connected to said slave processor, for servicing memory requests of said slave processor; (c) a shared memory storage means, connected to said master and said slave memory control units, and providing data storage areas accessible to said master and said slave memory control units.

Claim 3

-The memory control circuit of claim 1 which includes: (d) a control bus connecting said master and said slave memory control units for transmission of interrupt and control signals.

Claim 4

The memory control circuit of claim 2 wherein each of said master and slave memory control units includes: (3a) a local memory providing program and data storage, said local memory being directly addressable by addresses transmitted from the respective said master and said slave processors.

Claim 5

The memory control circuit of claim 3 wherein each of said master and slave memory control units further includes: (4a) access logic means for providing addresses to selected areas of said shared memory storage means; (4b) bus means to receive data from said shared memory storage means for transmission respectively to said master or said slave processor.

Claim 6

The memory control circuit of claim 4 wherein said access logic means includes: (5a) an arithmetic logic unit having a first input for receiving address data from said master/slave processor, and a second input for receiving address data from a base address register, said arithmetic logic unit operating to combine said first and second address inputs to transmit an address signal to said shared memory storage means; (5b) a base register means loaded by data from said master/slave processor and having an output to said arithmetic logic unit.

Claim 7

The memory control circuit of claim 4 wherein the memory control unit connected to said master processor includes: (6a) module select logic means for controlling whether said master processor or said slave processor will have priority of access to said shared memory storage means when simultaneous requests for access occur to the same address in said shared memory storage means.

Claim 8

The memory control circuit of claim 5 wherein said access logic means further includes: (7a) decoding means responsive to the four most significant bits of the incoming memory address in order to select whether the said local memory or the shared memory means is to be addressed.

Claim 9

The memory control circuit of claim 5 wherein said base register means includes: (8a) a first group of eight base registers; (8b) a record group of eight base registers; and wherein signals from said master/slave processor operate to select which group of base registers will be used and which base register will be selected.

Claim 10

The memory control card of claim 4 wherein each of said master and said slave memory control units includes: (9a) means to generate a WAIT signal to respectively stop said master/slave processor, said WAIT signal being generated when: (i) a memory control unit is writing into or reading from said shared memory means; or (ii) both said memory control units are simultaneously accessing said shared memory means.

Claim 11

In a processor-controller for a data communications network wherein said processor-controller executes data transfers between a main host computer and a plurality of line communication processors connected to remote data terminals via line adapters, and wherein said processor-controller provides a master processor, for controlling data transfers to/from said host computer, and provides a slave processor, for controlling data transfers to said line communication processors, a memory control circuit comprising: I. a master memory control unit and a slave memory control unit, each of said memory control units comprising: (a) local memory means connected to said processor via an I/O bus; (b) access logic circuitry for receiving address data via a memory address bus from said processor, and processing said address data to select a specific memory storage area in a shared memory storage means; (c) bus means connecting said processor and said memory control unit, said bus means including: (cl) a memory output data bus connecting the output of said local memory means to said processor; (c2) a memory address bus connecting said processor to said access logic circuitry; (c3) an I/O bus connecting said processor to said local memory means and to said access logic circuitry; (d) shared memory storage means having bus connection means which include: (dl) an address input bus from said access logic circuitry; (d2) a data output bus connected to said processor.

Claim 12

In a processor-controller for a data communications network wherein said processor-controller executes data transfers between a main host computer and a plurality of line communication processors connected to remote data terminals via line adapters, and wherein said processor-controller provides a master processor, for controlling data transfers to/from said host computer, and provides a slave processor, for controlling data transfers to said line communication processors, a memory control circuit comprising: I. a master memory control unit and a slave memory control unit, each of said memory control units comprising: (a) local memory means connected to said processor via an I/O bus; (b) access logic circuitry for receiving address data via a memory address bus from said processor, and processing said address data to select a specific memory storage area in a shared memory storage means; (c) bus means connecting said processor and said memory control unit, said bus means including: (cl) a memory output data bus connecting the output of said local memory means to said processor; (c2) a memory address bus connecting said processor to said access logic circuitry; (c3) an I/O bus connecting said processor to said local memory means and to said access logic circuitry; (d) shared memory storage means having bus connection means which include: (dl) an address input bus from said access logic circuitry; (d2) a data output bus connected to said processor.