EP0074305A2
Expired / Lapsed
EP
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Fault isolating memory decoder
Assignee: Fairchild Semiconductor Corp
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Filing: 1982-08-24
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Granted: —
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Expires: 2002-08-24
Abstract
Abstract Logic elements are added to a conventional decoder to allow one or more defective blocks of columns to be isolated and one or more redundant blocks of columns to be substituted. The redundant block of columns is programmed by non-volatile latches. A repair address is stored in the latches. When the decoded address to a block of columns is the same as the repair address, the redundant block of columns is selected and all other blocks of columns are de-selected. Normal column block addressing is unaffected when the decoded address is different from the repair address.
Inventors
- 👤 Andrew C. Tickle
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 05:35
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/785; G11C29/789
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
136 words
A method of testing a semiconductor memory circuit containing a plurality of blocks of columns of memory cells and at least one redundant block of columns of memory cells which is characterized by: selecting the address of each of said plurality of blocks of columns of memory cells in sequence and testing the status of each bit in each of said plurality of blocks of columns of memory cells during the time that said block of columns is addressed; and storing the address of the first block of columns of memory cells to contain one or more defective bits in a non-volatile memory latch, thereby to thereafter disable said first block of columns of memory cells containing one or more defective bits when its address is received and to substitute,therefor a redundant block of memory cells.
Claim 2
Independent Claim
136 words
A method of testing a semiconductor memory circuit containing a plurality of blocks of columns of memory cells and at least one redundant block of columns of memory cells which is characterized by: selecting the address of each of said plurality of blocks of columns of memory cells in sequence and testing the status of each bit in each of said plurality of blocks of columns of memory cells during the time that said block of columns is addressed; and storing the address of the first block of columns of memory cells to contain one or more defective bits in a non-volatile memory latch, thereby to thereafter disable said first block of columns of memory cells containing one or more defective bits when its address is received and to substitute,therefor a redundant block of memory cells.
Claim 3
Dependent Claim
81 words
A memory circuit comprising: a plurality of blocks of columns of memory cells; characterized by at least one redundant block of columns of memory cells contained on said memory circuit; and means for programming the address of a defective one of said blocks of columns containing at least one defective bit so as to select said one redundant block of columns for the storage or read-out of data whenever said defective one of said blocks of columns would normally be used.
Claim 4
Dependent Claim
81 words
A memory circuit comprising: a plurality of blocks of columns of memory cells; characterized by at least one redundant block of columns of memory cells contained on said memory circuit; and means for programming the address of a defective one of said blocks of columns containing at least one defective bit so as to select said one redundant block of columns for the storage or read-out of data whenever said defective one of said blocks of columns would normally be used.
Claim 5
Dependent Claim
68 words
The structure of Claim 2 characterized in that said means for programming comprises means for selecting one of a plurality of blocks of columns for storage or read-out of data; means for disabling said means for selecting when the address of the selected block of columns corresponds to the address of said defective one of said blocks of columns; and means for accessing a redundant block of columns.
Claim 6
Dependent Claim
66 words
The structure of Claim 3 characterized in that said means for disabling and said means for accessing includes means for storing the address of said defective one of said blocks of columns in a non-volatile form; and means responsive to the address of said defective one of said blocks of columns to thereby disable said means for selecting and instead address said redundant block of columns.
Claim 7
Dependent Claim
41 words
The structure of Claim 4 characterized in that said means for storing the address of said defective one of said blocks of columns comprises a plurality of non-volatile latches containing the address of said defective one of said blocks of columns.
References Cited (Backward Citations)
No citation records indexed.
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