EP0076494A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Data transmission bus system for a plurality of processors
Assignee: Hitachi Ltd
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Filing: 1982-10-01
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Granted: —
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Expires: 2002-10-01
Abstract
Abstract A data transmission system for transferring data between a plurality of processors (200A - 200G, 200Z, 2000) and between the processors and an input/output unit (303) through a common bus (301) has linkage units (300A - 300G, 300Z, 300L) between the processors and the bus and an address controller (302) to manage the bus. Each of the linkage units has a two-port random access memory (42A - 42G) for storing data necessary for the processor. The processor processes the data stored in the memory and writes a result of the processing in an output area of the memory. The processing of the processors and the data transfer through the bus are essentially separated and carried out independently.
Inventors
- 👤 Mitsuro Takakura
- 👤 Kazuhiko Shimoyama
- 👤 Tadashi Okamoto
- 👤 Noboru Azusawa
- 👤 Takenari Yoshida
- 👤 Yutaka Saito
- 👤 Takakazu Sakurai
- 👤 Susumu Kitani
- 👤 Yuji Kikuchi
- 👤 Yoshihiro Kamigane
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-25 07:46
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/161; G06F13/00; G06F13/14; G06F13/36; G06F13/362; G06F13/366
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
92 words
A data transmission system having a plurality of processors (200A - 200G, 200Z, 2000) and a bus (301) connected to said processors for transmitting data, comprising: linkage units (300A - 300G, 300Z, 300L) having memories for storing data, arranged between said processors and said bus; an address controller (302) for generating an address for the data transfer arranged between said processors and said bus; and means for selecting one of said linkage units as a data sending source and other linkage as receiving units by said address to effect the data transfer.
Claim 2
Dependent Claim
92 words
A data transmission system having a plurality of processors (200A - 200G, 200Z, 2000) and a bus (301) connected to said processors for transmitting data, comprising: linkage units (300A - 300G, 300Z, 300L) having memories for storing data, arranged between said processors and said bus; an address controller (302) for generating an address for the data transfer arranged between said processors and said bus; and means for selecting one of said linkage units as a data sending source and other linkage as receiving units by said address to effect the data transfer.
Claim 3
Dependent Claim
42 words
A data transmission system according to Claim 1 wherein said address controller includes a clock pulse generator (500) for generating clock pulses and a counter (501) for cyclically counting said clock pulses, the count of said counter being supplied as said address.
Claim 4
Dependent Claim
50 words
A data transmission system according to Claim 1 wherein said address controller includes a clock pulse generator (500) for generating clock pulses, a counter (501) for cyclically counting said clock pulses and an address memory (502) for supplying said address stored therein in accordance with the count of said counter.
Claim 5
Dependent Claim
21 words
A data transmission system according to Claim .1 wherein said memories of said linkage units are two port random access memories.
Claim 6
Dependent Claim
58 words
A data transmission system according to Claim 1 wherein each of said linkage units includes a memory (42A - 42G) for storing data from said processors and other linkage units and a transfer controller for decoding said address to send out the data stored in an output area of said memory only when its: own unit is selected.
Claim 7
Dependent Claim
29 words
A data transmission system according to Claim 1 wherein one of said processors is a back-up processor (200Z) for backing up one of other processors when it is down.
Claim 8
Dependent Claim
30 words
A data transmission system according to Claim 1 wherein one of said processor is a host computer (2000) which issues an instruction to back up one of the down processors.
Claim 9
Dependent Claim
130 words
A data transmission system having a plurality of processors (200A - 200G, 200Z, 2000), a common data input/output unit (303) and a common bus (301) for transmitting data between said processors and between said processors and said data input/output unit, said system further comprising: linkage units (300A - 300G, 300Z, 300L) arranged between said bus and said processors; and an address controller (302) for generating an address for data transfer through the bus between said linkage units; each of said linkage units including a memory (42A - 42G) for storing data supplied from the associated processor, other processors and said input/output unit and a transfer controller for decoding said address to send out the data stored in an output area of said memory only when its own unit is selected.
Claim 10
Dependent Claim
130 words
A data transmission system having a plurality of processors (200A - 200G, 200Z, 2000), a common data input/output unit (303) and a common bus (301) for transmitting data between said processors and between said processors and said data input/output unit, said system further comprising: linkage units (300A - 300G, 300Z, 300L) arranged between said bus and said processors; and an address controller (302) for generating an address for data transfer through the bus between said linkage units; each of said linkage units including a memory (42A - 42G) for storing data supplied from the associated processor, other processors and said input/output unit and a transfer controller for decoding said address to send out the data stored in an output area of said memory only when its own unit is selected.
Claim 11
Dependent Claim
20 words
A data transmission system according to Claim 8 wherein said memories of said linkage units are two-port random access memories.
Claim 12
Dependent Claim
58 words
A data transmission system according to Claim 8 wherein said address controller includes an address counter (501) for counting clock pulses, an address memory (502) for supplying an address in accordance with the count of said counter and a decoder for decoding said address to supply a gate control signal to said transfer controllers of said linkage units.
Claim 13
Dependent Claim
152 words
ll. A data transmission system having a bus (301) for transmitting data, a plurality of computers (200A - 200G, 200Z, 2000) for transmitting the data through said bus and an input/output unit (303) connected to said bus, said system further comprising: linkage units (300A - 300G, 300Z, 300L) arranged between said computers and said bus, each of said linkage units including a memory (42A - 42B) for storing the data and input/output gates for supplying the content of said memory to said bus and the data sent out to said bus to said memory in response to a data transfer command; .an address controller (302) for issuing the data transfer command to manage the data transfer between said linkage units and between said linkage units and said input/output units; and means for transferring the data between said input/output unit and said computers and between said computers according to the data transfer command.
Claim 14
Dependent Claim
152 words
ll. A data transmission system having a bus (301) for transmitting data, a plurality of computers (200A - 200G, 200Z, 2000) for transmitting the data through said bus and an input/output unit (303) connected to said bus, said system further comprising: linkage units (300A - 300G, 300Z, 300L) arranged between said computers and said bus, each of said linkage units including a memory (42A - 42B) for storing the data and input/output gates for supplying the content of said memory to said bus and the data sent out to said bus to said memory in response to a data transfer command; .an address controller (302) for issuing the data transfer command to manage the data transfer between said linkage units and between said linkage units and said input/output units; and means for transferring the data between said input/output unit and said computers and between said computers according to the data transfer command.
References Cited (Backward Citations)
No citation records indexed.
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