EP0081387A1 — Apparatus for selectively compensating burst erro…

Claim 1

Independent Claim 308 words

Apparatus for selectively compensating burst errors of variable length in successive data words, the apparatus comprising: an input (12, 16 to 19) for receiving said successive data words; identifying means (13 to 15) for identifying which data words are erroneous and correct, respectively; interpolating means (20) for producing an interpolated data word by averaging two data words supplied thereto; sensing means (36) for sensing the following conditions: (a) the presence of an erroneous data word preceded and followed, respectively, by correct data words, (b) the presence of a plurality of successive erroneous data words preceded and followed, respectively, by correct data words, and (c) the presence of a predetermined number of successive erroneous data words preceded by a correct data word; supply means (22, 25) responsive to sense said conditions (a) and (b) for supplying to said interpolating means (20) the preceding and following correct data words of the respectively sensed conditions; interpolation control means coupled to said interpolating means (20) and to said sensing means (36) and responsive to said condition (a) for controlling said interpolating means (20) to operate once, said interpolation control means being responsive to said condition (b) for controlling said interpolating means to operate a plurality of times to produce a plurality of interpolated data words; and replacement means (21, 23) coupled to said interpolating means (20) and to said sensing means (36) and responsive to said condition (a) for replacing the erroneous data word with the interpolated data word, said replacement means (21, 23) being responsive to said condition (b) for replacing the plurality of successive erroneous data words with respective ones of the plurality of interpolated data words, and said replacement means (21, 23) being responsive to said condition (c) for replacing at least the first of said predetermined number of successive erroneous data words with the preceding correct data word.

Claim 2

Dependent Claim 308 words

Apparatus for selectively compensating burst errors of variable length in successive data words, the apparatus comprising: an input (12, 16 to 19) for receiving said successive data words; identifying means (13 to 15) for identifying which data words are erroneous and correct, respectively; interpolating means (20) for producing an interpolated data word by averaging two data words supplied thereto; sensing means (36) for sensing the following conditions: (a) the presence of an erroneous data word preceded and followed, respectively, by correct data words, (b) the presence of a plurality of successive erroneous data words preceded and followed, respectively, by correct data words, and (c) the presence of a predetermined number of successive erroneous data words preceded by a correct data word; supply means (22, 25) responsive to sense said conditions (a) and (b) for supplying to said interpolating means (20) the preceding and following correct data words of the respectively sensed conditions; interpolation control means coupled to said interpolating means (20) and to said sensing means (36) and responsive to said condition (a) for controlling said interpolating means (20) to operate once, said interpolation control means being responsive to said condition (b) for controlling said interpolating means to operate a plurality of times to produce a plurality of interpolated data words; and replacement means (21, 23) coupled to said interpolating means (20) and to said sensing means (36) and responsive to said condition (a) for replacing the erroneous data word with the interpolated data word, said replacement means (21, 23) being responsive to said condition (b) for replacing the plurality of successive erroneous data words with respective ones of the plurality of interpolated data words, and said replacement means (21, 23) being responsive to said condition (c) for replacing at least the first of said predetermined number of successive erroneous data words with the preceding correct data word.

Claim 3

Dependent Claim 78 words

Apparatus according to claim 1 wherein said interpolation control means includes means responsive to said condition (b) temporarily to store a pseudo interpolated data word produced by said interpolating means (20) in response to the averaging of said preceding and following data words, and means for supplying the temporarily stored pseudo interpolated data word and one of said preceding and following data words to said interpolating means (20) for averaging therein to produce a first interpolated data word.

Claim 4

Dependent Claim 45 words

Apparatus according to claim 2 wherein said interpolation control means further includes means for supplying said first interpolated data word and the other of said preceding and following data words to said interpolating means (20) and averaging therein to produce a second interpolated data word.

Claim 5

Dependent Claim 48 words

Apparatus according to claim 3 wherein said replacement means (21, 23) includes means for replacing a first of two successive erroneous data words with said first interpolated data word, and means for replacing a second of said two successive erroneous data words with said second interpolated data word.

Claim 6

Dependent Claim 30 words

Apparatus according to claim 1 wherein the predetermined number of successive erroneous data words of said condition (c) exceeds the plurality of successive erroneous data words of said condition (b).

Claim 7

Dependent Claim 38 words

Apparatus according to claim 1 wherein each successive data word is accompanied by an error flag; and said identifying means includes flag storage means (13 to 15) for storing the error flags of said received successive data words.

Claim 8

Dependent Claim 55 words

Apparatus according to claim 6 wherein said input includes data word register means (16 to 19) having a plurality of stages for storing respective data words; and shift clock means coupled to said data word register means (16 to 19) for shifting a plurality of data words into successive stages in successive shift clock period.

Claim 9

Dependent Claim 54 words

Apparatus according to claim 7 wherein said flag storage means comprises flag register means (13 to 15) having a plurality of stages for storing respective error flags of said data words and coupled to said shift clock means for shifting successive error flags into successive flag register stages in said successive shift clock periods.

Claim 10

Dependent Claim 49 words

Apparatus according to claim 8 wherein said sensing means includes means (36) coupled to the stages of said flag register (13 to 15) for detecting the conditions of the respective error flags stored in said flag register (13 to 15), thereby sensing said conditions (a), (b) and (c), respectively.

Claim 11

Dependent Claim 53 words

Apparatus according to claim 9 wherein said supply means includes selector means (22, 25) coupled to preselected stages of said data word register means (16 to 19) for supplying the data words stored in selected stages to said interpolating means (20) as a function of the detected conditions of the stored error flags.

Claim 12

Dependent Claim 63 words

Apparatus according to claim 10 wherein said interpolation control means includes pulse generating means for generating one and for generating a plurality of averaging pulses during a shift clock period, and averaging pulse supply means responsive to the detected conditions of the stored error flags selectively to supply said one averaging pulse or said plurality of averaging pulses to said interpolating means (20).

Claim 13

Dependent Claim 58 words

Apparatus according to claim 11 wherein said data word register means (16 to 19) includes four stages and said flag register (13 to 15) includes three stages for storing the error flags of the first, second and third data words respectively stored in the first, second and third stages of said data word register means (16 to 19).

Claim 14

Dependent Claim 94 words

Apparatus according to claim 12 wherein said selector means comprises a first selector (22) coupled to said first and second stages (16, 17) of said data word register means (16 to 19) for selectively supplying to said interpolating means (20) the data word stored in said first or second stages (16, 17), and a second selector (25) coupled to said third and fourth stages (18, 19) of said data register means (16 to 19) for selectively supplying to said interpolating means (20) the data word stored in said third or fourth stage (18, 19).

Claim 15

Dependent Claim 126 words

Apparatus according to claim 13 wherein said first and second selectors (22, 25) and said averaging pulse supply means are responsive to the detection of an error condition of the error flag stored in the second stage (14) of said error flag register (13 to 15) and the detection of a correct condition of the error flag stored in the third stage (15) of said error flag register (13 to 15) to supply to said interpolating means (20) the data words stored in the first and third stages (16, 18) of said data word register means (16 to 19), and to supply said one averaging pulse to said interpolating means (20), whereby an interpolated word derived from the average of the supplied data words is produced.

Claim 16

Dependent Claim 149 words

Apparatus according to claim 13 wherein said replacement means includes a first switch (21) for selectively supplying to said second stage (17) of said data word register means (16 to 19) either the data word stored in said first stage (16) or the interpolated word produced by said interpolating means (20), said first switch (21) being responsive to detected said condition (a) to supply said interpolated data word to said second stage (17) of said data word register means (16 to 19) for storage therein prior to the beginning of the next shift clock period and to change over the error flag stored in the second stage (14) of said error flag register (13 to 15) from an error condition to a correct condition; and said replacement means further includes a second switch (23) coupled to the third stage (18) of said data word register means (16 to 19).

Apparatus for selectively compensating burst errors of variable length in successive data words

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