EP0084460A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Improvements in and relating to computer memory control systems
Assignee: Tandem Computers Inc
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Filing: 1983-01-19
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Granted: —
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Expires: 2003-01-19
Abstract
Abstract A memory system (11) for a computer detect data errors, address errors and operation errors to increase the reliability of data stored in the memory system. Address errors are detected by encoding address parity information into the data check field of each memory location. A signal is generated in each memory module (21) indicating the status of operations of that memory module and is transmitted to the processor subsystem (13,15,17 & 37) of the computer for comparison with a signal indicating the status of operations of the processor subsystem to ensure that all memory modules (21) and the memory control in the processor are receiving the same commands.
Inventors
- 👤 Richard Anthony Humphrey
- 👤 Steven Derek Fisher
- 👤 Steven Warren Wierenga
- 👤 Jon Sjostedt
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 23:45
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1012; G06F11/1016; G06F11/0703; G06F11/0751; G11; G11C; G11C29/00; G11C29/02
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
154 words
A computer memory control system (11) comprising, a processor subsystem and a memory subsystem, characterised in that the processor subsystem comprises a map/memory control means (13), error correction code logic means (15) and operation check logic means (17), and in that the memory subsystem comprises a memory module (21) having a storage array (55), bus means (33) connecting the storage array (55) to the map/memory control means (13) and error correction code logic means (15), timing and control logic means (59), a control bus (39) connecting the timing and control logic means to the map/memory control means (13), an operation state bus (53) connected to the operation check logic means (17),and memory'module operation state machine means (61) for generating a signal indicating the status of operations of the memory module (21) and for transmitting that signal to the operation check logic means (17) for comparison to the status of operations of the processor subsystem.
Claim 2
Dependent Claim
154 words
A computer memory control system (11) comprising, a processor subsystem and a memory subsystem, characterised in that the processor subsystem comprises a map/memory control means (13), error correction code logic means (15) and operation check logic means (17), and in that the memory subsystem comprises a memory module (21) having a storage array (55), bus means (33) connecting the storage array (55) to the map/memory control means (13) and error correction code logic means (15), timing and control logic means (59), a control bus (39) connecting the timing and control logic means to the map/memory control means (13), an operation state bus (53) connected to the operation check logic means (17),and memory'module operation state machine means (61) for generating a signal indicating the status of operations of the memory module (21) and for transmitting that signal to the operation check logic means (17) for comparison to the status of operations of the processor subsystem.
Claim 3
Dependent Claim
76 words
A system as claimed in claim 1 characterised in that the error correction code logic means (15) include a processor subsystem operation state machine means for generating'a signal representing the status of operations of the processor subsystem and compare logic means for comparing the signal generated by the memory module operation state machine means (61) and the processor subsystem operation state machine means and for producing an operation check error signal output to the processor subsystem.
Claim 4
Dependent Claim
25 words
A system as claimed in claim 1 or 2 characterised in that the error correction code logic means (15) include address error detection means (73).
Claim 5
Dependent Claim
36 words
A system as claimed in claim 3 characterised in that the address error detection means (73) include address parity generator means (86) for encoding address parity information into a data check field of each memory location.
Claim 6
Independent Claim
55 words
A system as claimed in any one of claims 1 to 4 characterised in that the error correction code logic means (15) include syndrome means (85) for identifying address errors as well as data errors indicated in the check field during a read operation on a data code word read from the storage array (55).
Claim 7
Dependent Claim
148 words
A control memory module for a computer system processor module of the kind having a map/memory control (13), error correction code logic (15) and operation check logic (17), characterised in that the memory module comprises a semiconductor storage array (55), timing and control logic (59), bus means for connecting the storage array (55) to the map/memory control (13) and error correction code logic (15) and for connecting the timing and control logic (59) to the map/memory control (13), an operation state bus (53) connectible to the operation check logic (17) of the processor module, and operation state machine means (67) associated with the operation state bus and fhe timing and control logic (59) for generating a signal indicating the status of operations of the memory module and for transmitting that signal to the operation check logic (17) for comparison to the status of operations of the processor module.
Claim 8
Dependent Claim
148 words
A control memory module for a computer system processor module of the kind having a map/memory control (13), error correction code logic (15) and operation check logic (17), characterised in that the memory module comprises a semiconductor storage array (55), timing and control logic (59), bus means for connecting the storage array (55) to the map/memory control (13) and error correction code logic (15) and for connecting the timing and control logic (59) to the map/memory control (13), an operation state bus (53) connectible to the operation check logic (17) of the processor module, and operation state machine means (67) associated with the operation state bus and fhe timing and control logic (59) for generating a signal indicating the status of operations of the memory module and for transmitting that signal to the operation check logic (17) for comparison to the status of operations of the processor module.
Claim 9
Dependent Claim
132 words
A memory module as claimed in claim 6 adapted as an address error apparatus for detecting address errors in the computer system wherein the error correction code logic (15) which encodes a data check field at each memory location for detection of data errors in the data field of each memory location, the module being characterised by encoding means (86) for encoding address parity information into the data check field at each memory location on a write operation, read address means (84) for reading address parity information from the memory array on a subsequent read operation, and comparator means.(83) for comparing the parity information encoded during the write operation with the parity information generated during the read operation to generate a syndrome (85) that indicates the type of address error, if any.
Claim 10
Dependent Claim
54 words
. A module as claimed in claim 7 characterised in that the error correction code logic (15) includes parity tree means (87) for parity detection of data errors and in that the module is included in the error correction code logic (15) of the computer system as part of the parity tree means (87).
Claim 11
Dependent Claim
104 words
A computer memory control system for protecting data integrity in the main memory of a computer and characterised by a word organized memory (55) with each word location having a data field and a check field, data error detecting means for detecting data and check errors by a syndrome code encoded in the check field of each word, address error detection means for detecting address errors by encoding address parity information into the check field of each word, and operations error check means for detecting any difference in the sequence of operations between a memory subsystem and a processor subsystem of the computer system.
Claim 12
Dependent Claim
104 words
A computer memory control system for protecting data integrity in the main memory of a computer and characterised by a word organized memory (55) with each word location having a data field and a check field, data error detecting means for detecting data and check errors by a syndrome code encoded in the check field of each word, address error detection means for detecting address errors by encoding address parity information into the check field of each word, and operations error check means for detecting any difference in the sequence of operations between a memory subsystem and a processor subsystem of the computer system.
Claim 13
Dependent Claim
29 words
A computer memory control system as claimed in claim 9 characterised in that the data error detecting means comprise parity tree means (87) for parity detection of data errors.
Claim 14
Dependent Claim
31 words
A computer memory control system as claimed in claim 10 characterised in that the address error detection means use the same parity tree means (87) as the data error detecting means.
Claim 15
Dependent Claim
104 words
A computer memory control system as claimed in claim 11 characterised in that the operations error detecting means comprise a first operation state machine means (67) in the processor subsystem for generating a signal indicating the status of operations in the processor subsystem, an additional operation state machine means (61) in each memory module of the memory subsystem for generating a signal indicating the status of operations in the memory module, and compare logic means (69) for comparing the signal from each memory module with the signal from the processor subsystem and for producing an operation check error signal output to the processor subsystem.
Claim 16
Independent Claim
78 words
A method of detecting address errors in a memory system of a computer of the kind having a word organized storage array (55) with each word comprising a data field and a check field, said method being characterised by encoding a data error detecting syndrome code into the check field and encoding address error parity information into the check field so as to detect any address errors by the same syndrome code as used for data error detection.
Claim 17
Independent Claim
78 words
A method of detecting address errors in a memory system of a computer of the kind having a word organized storage array (55) with each word comprising a data field and a check field, said method being characterised by encoding a data error detecting syndrome code into the check field and encoding address error parity information into the check field so as to detect any address errors by the same syndrome code as used for data error detection.
Claim 18
Independent Claim
82 words
A method of detecting operations errors of a memory module connectible to a computer system processor module, said method being characterised by generating at the memory module a signal indicating the status of operations of said module, simultaneously generating at the processor module a signal indicating the status of operations of the processor module, transmitting the status signal of the memory module to the processor module, comparing the two status signals and producing an operation check error signal to the processor module.
Claim 19
Independent Claim
82 words
A method of detecting operations errors of a memory module connectible to a computer system processor module, said method being characterised by generating at the memory module a signal indicating the status of operations of said module, simultaneously generating at the processor module a signal indicating the status of operations of the processor module, transmitting the status signal of the memory module to the processor module, comparing the two status signals and producing an operation check error signal to the processor module.
References Cited (Backward Citations)
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