Nonvolatile semiconductor memory circuit

Claim 2

A nonvolatile semiconductor memory circuit (10) which is provided with a plurality of bit lines (B), a plurality of word lines (13), nonvolatile semiconductor memory cells (14) located at intersections of the bit lines (B) and word lines (13) and formed by MOS transistors (14) having a floating gate (FG) and a control gate (CG), a bias circuit (11) which supplies a read-out voltage to the control gate (CG) of a selected nonvolatile semiconductor memory cell (14), and sense amplifiers (18) each having an input which receives read-out data from the selected nonvolatile semiconductor memory cell (14) and an output which outputs amplified read-out data, the bias circuit (11) including a dummy cell (42) having substantially the same construction as the nonvolatile semiconductor memory cells, characterized in that the bias circuit (11) also includes a dummy sense amplifier (41) which has substantially the same construction as the sense amplifier (18) and which supplies current to the dummy cell (42), the output (Vout) of the bias circuit (11) providing negative feed back in proportion to the output of the dummy sense amplifier (41) to the control gate (CG) of the dummy cell (42) to maintain the current (i) flowing through it constant.

Claim 3

A nonvolatile semiconductor circuit according to claim 1, wherein the bias circuit (11) also includes a voltage setting circuit (43) connected between an output of the dummy sense amplifier (41) and the output (V out ) of the bias circuit (11), wherein the dummy cell (42) is formed by a first transistor (44) having a floating gate (FG) and a control gate (CG) and a second transistor (45) which is connected to the first transistor (44), wherein dummy sense amplifier (41) is formed by a first circuit composed of a first depletion-type transistor (41a), a second depletion-type transistor (41b), and a first enhancement-type transistor (41c), connected in series, a second circuit composed of a second enhancement-type transistor (41d) having a drain connected to the drain of the first depletion-type transistor (41 a), a gate connected to the connection point of the first depletion-type transistor (41a) and the second depletion-type transistor (41 b), and a source connected to the gate of the first enhancement-type transistor (41c) and the drain of the second transistor (45) in the dummy cell (42), and a third circuit composed of a third depletion-type transistor (41c) and a third enhancement-type transistor (41f) connected in series, the third enhancement type transistor (41f) having a gate connected to the connection point of the second depletion-type transistor (41b) and the first enhancement-type transistor (41c), and wherein the voltage setting circuit (43) is formed by a first series circuit composed of a fourth depletion-type transistor (43a) and a fourth enhancement-type transistor (43b) having a gate connected to the connection point of the third depletion-type transistor (41c) and the third enhancement-type transistor (41f) and a second series circuit composed of a fifth depletion-type transistor (43c) and a fifth enhancement-type transistor (43d) having a gate connected to the connection point of the fourth depletion-type transistor (43a) and the fourth enhancement-type transistor (43b), and the connection point of the fifth depletion-type transistor (43c) and the fifth enhancement-type transistor (43d) forms the output (V o"t ) and is connected to the control gate (CG) of the first transistor (44) in the dummy cell (42).