← Back to Patent Explorer
EP0096455A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Multilayer interconnection structure for semiconductor device

Assignee: Toshiba Corp
•
Filing: 1983-04-08
•
Granted: —
•
Expires: 2003-04-08
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A multilayer interconnection structure for a semiconductor device has interconnection layers superposed on each other on the surface of a semiconductor substrate with an insulating layer interposed therebetween. Connection between the desired interconnection layers or between the desired interconnection layer and semiconductor substrate is effected by means of a contact hole formed in the respective insulating layers. Two upper and lower interconnection layers intersect each other above the contact holes, and the contact hole (8a, 8b, 8c, 8d) does not overlap part of the traverse region of the upper interconnection layer (7) in the intersecting section.

Inventors

  • 👤 Yukihiro Ushiku

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-30 15:26
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/42

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 105 words
A multilayer interconnection structure for a semiconductor device wherein a plurality of interconnection layers are deposited on the surface of a semiconductor substrate with an insulating layer interposed between the adjacent interconnection layers; connection between the desired interconnection layers or between the desired interconnection layer and semiconductor substrate is assured by means of a contact hole formed in the respective insulating layers; two upper and lower interconnection layers intersect each other above the contact hole, characterized in that the con- . tact hole (8a, 8b, 8c, 8d) does not overlap part of the traverse region of the upper interconnection layer (7) in the intersecting section.
Claim 2
Dependent Claim 105 words
A multilayer interconnection structure for a semiconductor device wherein a plurality of interconnection layers are deposited on the surface of a semiconductor substrate with an insulating layer interposed between the adjacent interconnection layers; connection between the desired interconnection layers or between the desired interconnection layer and semiconductor substrate is assured by means of a contact hole formed in the respective insulating layers; two upper and lower interconnection layers intersect each other above the contact hole, characterized in that the con- . tact hole (8a, 8b, 8c, 8d) does not overlap part of the traverse region of the upper interconnection layer (7) in the intersecting section.
Claim 3
Dependent Claim 34 words
The multilayer interconnection structure according to claim 1, characterized in that a plurality of contact holes (8a, 8b, 8c, 8d) are linearly arranged in the direction in which the lower interconnection layer (5) extends.
Claim 4
Dependent Claim 35 words
The multilayer interconnection structure according to claim I, characterized in that the contact hole (10) extending along the lower interconnection layer (5) has a shorter length than the width of the upper interconnection layer (7).

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag