EP0100572A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Electrically erasable PROM-cell
Assignee: Koninklijke Philips NV
•
Filing: 1983-07-19
•
Granted: —
•
Expires: 2003-07-19
Abstract
Abstract In an EEPROM memory cell of the kind which relies on tunneling action through a thin oxide layer to store charge on a floating gate, the floating gate and the channel regions of the memory cell are provided with additional doping of the same kind as in the substrate in order to raise the virgin state threshold voltage of the memory cell to a high positive value, such as 4 volts. Additionally, the overlap area between the control gate and the floating gate is reduced to the extent that the capacitance between the floating gate and the control gate is substantially equal to the capacitance between the floating gate and the substrate during programming, but the effective capacitance between the floating gate and the substrate is greatly reduced during erase mode. As a result, little or no tunneling occurs during programming and the threshold voltage level is the same as the virgin threshold value of the memory cell. However, during erase very efficient tunneling occurs from the floating gate to the substrate and the threshold voltage level decreases to a negative value. The difference between positive and negative values of the threshold voltage is comparable to that of conventional memory cells.
Inventors
- 👤 Parviz Keshtbod
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 16:40
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0441; H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/683; H10B; H10B69/00
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
304 words
A memory device, comprising: a body of semiconductive material of first conductivity type; first and second regions of second conductivity type spaced apart in said body by a first channel region; a floating gate overlying said first channel region; a first insulating layer separating said floating gate from said first channel region and having a portion which overlies a part of said first channel region and is thinner than the remainder thereof; a control gate overlying said floating gate; a second insulating layer of greater thickness than the thin portion of said first insulating layer separating said control gate from said floating gate; characterized in that a third region of second conductivity type in said body spaced apart from said second region by a second channel region is provided, the second channel region being covered also by said first insulating layer, said floating gate overlying also said second channel region, and being separated therefrom by said first insulating layer, said first and second channel regions having an additional sur- . face doping of first conductivity type and said floating gate having a doping of first conductivity type to raise the virgin state threshold voltage of said first and second channel regions; the areas of said floating and control gates and the thicknesses of said first and second insulating layers being so proportioned that when a programming voltage is applied between said control gate and said semiconductive body the capacitance between said floating gate and said control gate is substantially equal to the capacitance between said floating gate and said semiconductive body, and when an erase voltage of opposite polarity is applied between said control gate and said semiconductive body, the effective capacitance between said floating gate and said semiconductive body is substantially less than the capacitance between said floating gate and said control gate.
Claim 2
Dependent Claim
304 words
A memory device, comprising: a body of semiconductive material of first conductivity type; first and second regions of second conductivity type spaced apart in said body by a first channel region; a floating gate overlying said first channel region; a first insulating layer separating said floating gate from said first channel region and having a portion which overlies a part of said first channel region and is thinner than the remainder thereof; a control gate overlying said floating gate; a second insulating layer of greater thickness than the thin portion of said first insulating layer separating said control gate from said floating gate; characterized in that a third region of second conductivity type in said body spaced apart from said second region by a second channel region is provided, the second channel region being covered also by said first insulating layer, said floating gate overlying also said second channel region, and being separated therefrom by said first insulating layer, said first and second channel regions having an additional sur- . face doping of first conductivity type and said floating gate having a doping of first conductivity type to raise the virgin state threshold voltage of said first and second channel regions; the areas of said floating and control gates and the thicknesses of said first and second insulating layers being so proportioned that when a programming voltage is applied between said control gate and said semiconductive body the capacitance between said floating gate and said control gate is substantially equal to the capacitance between said floating gate and said semiconductive body, and when an erase voltage of opposite polarity is applied between said control gate and said semiconductive body, the effective capacitance between said floating gate and said semiconductive body is substantially less than the capacitance between said floating gate and said control gate.
Claim 3
Dependent Claim
77 words
A memory device according to Claim 1, characterized in that it further includes a fourth region of second conductivity type in said body spaced apart from said first region by a third channel region, a select gate, and a third insulating layer separating said select gate from said third channel region, said first and third regions, said third channel region and said select gate constituting a select transistor in series with said first and second channel regions.
Claim 4
Dependent Claim
25 words
A memory device according to Claim 2, characterized in that said first, second, and third channel regions are aligned lengthwise along a common linear axis.
Claim 5
Dependent Claim
39 words
A memory device according to Claim 1, characterized in that said floating gate and said control gate are rectangularly annular in shape and are formed with a ' central rectangular opening overlying said second region of second conductivity type.
Claim 6
Dependent Claim
27 words
A memory device according to Claim 1, characterized in that said floating gate overlies side diffused regions of said first and second regions of second conductivity type.
Claim 7
Dependent Claim
46 words
A memory device according to Claim 1, characterized in that the doping of said first and second channel regions and the doping of said floating gate are such that the virgin state threshold voltage of said second channel regions is about 3 to 4 volts positive.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.