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EP0103236A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Logical circuit

Assignee: Toshiba Corp
•
Filing: 1983-08-31
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Granted: —
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Expires: 2003-08-31
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Abstract

Abstract A logic circuit comprises a first and second circuit. The first circuit consists of at least one first conductivity-type MOSFET (14, 23, 33, 43) whose gate is connected to an input terminal, and which is connected at one end to an output terminal. The second circuit consists of at least one second conductivity-type MOSFET (15, 24, 34, 44) whose gate is connected to the input terminal, and which is connected at one end to the output terminal. The gate of the second conductivity-type MOSFET (15,24,34,44) is connected to the input terminal, and one end of this MOSFET is connected to the output terminal. The logical circuit further comprises a depletion-type MOSFET (13, 21, 31, 41) of the second conductivity type and a depletion-type MOSFET (16, 22, 32, 42) of the first conductivity type. The depletion-type MOSFET (13, 21, 31, 41) of the second conductivity type has a threshold voltage the absolute value of which is larger than that of the first conductivity-type MOSFET (14, 23, 33, 43), is connected between the other end of the first conductivity-type MOSFET (14, 23, 33, 43) and a first power source, and has its gate connected to the output terminal. The depletion-type MOSFET (16, 22, 32, 42) of the first conductivity type has a threshold voltage the absolute value of which is larger than that of the second conductivity-type MOSFET (15, 24, 34, 44) is connected between the other end of the second conductivity-type MOSFET (15, 24, 34, 44) and a second power source, and has its gate connected to the output terminal.

Inventors

  • 👤 Hideharu Koike

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-29 17:17
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/354; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/0948; H03K19/09482; H03K19/09485; H03K3/356; H03K3/356104; H03K3/3565

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 204 words
A logical circuit having a first circuit consisting of at least one first conductivity-type MOSFET (14, 23, 33, 43) whose gate is connected to an input terminal, and having a second circuit consisting of at least one second conductivity-type MOSFET (15, 24, 34, 44) whose gate is connected to said input terminal, said first and second circuits being connected at one end to an output terminal and at the other end to a first power source and a second power source, respectively; said logical circuit being characterized by comprising: a depletion-type MOSFET (13, 21, 31, 41) of the second conductivity type, which has a threshold voltage, the absolute value of which is larger than that of said first conductivity-type MOSFET, which MOSFET is interposed between the other end of said first circuit and said first power source, and whose gate is connected to said output terminal; and a depletion-type MOSFET (16, 22, 32, 42) of the first conductivity type, which has a threshold voltage the absolute value of which is larger than that of said second conductivity-type MOSFET, which MOSFET is interposed between the other end of said second circuit and said second power source, and whose gate is connected to said output terminal.
Claim 2
Dependent Claim 204 words
A logical circuit having a first circuit consisting of at least one first conductivity-type MOSFET (14, 23, 33, 43) whose gate is connected to an input terminal, and having a second circuit consisting of at least one second conductivity-type MOSFET (15, 24, 34, 44) whose gate is connected to said input terminal, said first and second circuits being connected at one end to an output terminal and at the other end to a first power source and a second power source, respectively; said logical circuit being characterized by comprising: a depletion-type MOSFET (13, 21, 31, 41) of the second conductivity type, which has a threshold voltage, the absolute value of which is larger than that of said first conductivity-type MOSFET, which MOSFET is interposed between the other end of said first circuit and said first power source, and whose gate is connected to said output terminal; and a depletion-type MOSFET (16, 22, 32, 42) of the first conductivity type, which has a threshold voltage the absolute value of which is larger than that of said second conductivity-type MOSFET, which MOSFET is interposed between the other end of said second circuit and said second power source, and whose gate is connected to said output terminal.
Claim 3
Dependent Claim 23 words
A logical circuit according to claim 1, characterized in that said MOSFETs whose gates are connected to said input terminal are enhancement-type MOSFETs.
Claim 4
Dependent Claim 23 words
A logical circuit according to claim 1, characterized in that said MOSFETs whose gates are connected to said input terminal are depletion-type MOSFETs.
Claim 5
Dependent Claim 19 words
A logical circuit according to claim 1, characterized in that said first and second circuits form a complementary-type inverter.
Claim 6
Dependent Claim 21 words
A logical circuit according to claim 1, charac- teirzed in that said first and second circuits form a complementary-type NOR circuit.
Claim 7
Dependent Claim 20 words
A logical circuit according to claim 1, characterized in that said first and second circuits form a complementary-type NAND circuit.
Claim 8
Dependent Claim 28 words
A logical circuit according to claim 1, characterized by further comprising a crystal oscillator including a crystal oscillating element (45) interposed between said input and said output terminals.
Claim 9
Dependent Claim 53 words
A logical circuit according to claim 4, characterized in that two sets of inverters (20, 30) are reversely connected in parallel, and each output is connected to a digit line through a transfer gate (25, 35) whose switching is controlled in accordance with a signal on a word line, thereby constituting a memory.

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