EP0107010A2
Expired / Lapsed
EP
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Video display system using serial/parallel acces memories
Assignee: Texas Instruments Inc
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Filing: 1983-09-14
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Granted: —
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Expires: 2003-09-14
Abstract
Abstract A video display system employs a memory arrangement for the video data which is sequentially accessed for serial read-out of the bit-mapped video information at a high clock rate, and also randomly accessed in parallel by a microcomputer for generating and updating the information to be displayed. Parallel access to the memory by the microcomputer can occur while the serial video data is being clocked out, so microcomputer I/O and video output conflict only a very minimum amount. Dynamic MOS RAMs with a serial register added provide this dual port memory.
Inventors
- 👤 Kevin C. Mcdonough
- 👤 David S. Laffitte
- 👤 John Mark Hughes
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 22:39
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/36; G09G5/39; G09G2360/00; G09G2360/12; G09G2360/126
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
160 words
A video display system comprising: a video display having raster scanning means and a video signal input for instantanously determining the brightness and/or color of display on a screen, a bit-mapped video memory consisting of a memory array including a plurality of rows and columns of read/write memory cells in a semiconductor substrate, addressing means for addressing the array, and means for accessing the array by two separate data ports, one port including a serial register having a serial output connected to said video signal input the register having a parallel input connected to said array for loading the register with video data bits from the array, the other port being a bit-parallel port for accessing the array for read and write, and a microprocessor device having parallel data/address bus means for supplying addresses to the addressing means and for accessing the data in said array via said bit parallel port to update the video information in the bit-mapped memory.
Claim 2
Dependent Claim
160 words
A video display system comprising: a video display having raster scanning means and a video signal input for instantanously determining the brightness and/or color of display on a screen, a bit-mapped video memory consisting of a memory array including a plurality of rows and columns of read/write memory cells in a semiconductor substrate, addressing means for addressing the array, and means for accessing the array by two separate data ports, one port including a serial register having a serial output connected to said video signal input the register having a parallel input connected to said array for loading the register with video data bits from the array, the other port being a bit-parallel port for accessing the array for read and write, and a microprocessor device having parallel data/address bus means for supplying addresses to the addressing means and for accessing the data in said array via said bit parallel port to update the video information in the bit-mapped memory.
Claim 3
Dependent Claim
35 words
A system according to claim 1 including clocking means for defining a cycle time for the microcomputer and a clock rate for shifting video data bits out of said register to said video signal input.
Claim 4
Dependent Claim
42 words
A system according to claim 2 wherein the microprocessor device accesses said memory array via said addressing means and said bit-parallel port while said clocking means is causing the shifting of video data bits from the register to the video signal input.
Claim 5
Dependent Claim
42 words
A system according to claim 3 wherein the micrcomputer device accesses multi-bit data words in the memory array in parallel in an access time much less than a time period required to shift all of said video data bits from the register.
Claim 6
Dependent Claim
49 words
A system according to claim 4 wherein said serial register is loaded in parallel from said memory array in no more than about said cycle time, then is clocked out in serial at said clock rate in said time period which is many times greater than said cycle time.
Claim 7
Dependent Claim
98 words
An electronic system comprising: utilization means requiring a serial data input at a high bit rate, a shared dual-port memory including addressing means for addressing the memory, serial and parallel data accessing means for accessing the memory by two separate data ports, one port including a serial register for supplying said serial data input of the utilization means, the other port providing bit-parallel access to the memory, a microprocessor device having parallel data/address bus means for supplying addresses to the addressing means of the memory and for reading from and writing into said memory via said other port.
Claim 8
Dependent Claim
98 words
An electronic system comprising: utilization means requiring a serial data input at a high bit rate, a shared dual-port memory including addressing means for addressing the memory, serial and parallel data accessing means for accessing the memory by two separate data ports, one port including a serial register for supplying said serial data input of the utilization means, the other port providing bit-parallel access to the memory, a microprocessor device having parallel data/address bus means for supplying addresses to the addressing means of the memory and for reading from and writing into said memory via said other port.
References Cited (Backward Citations)
No citation records indexed.
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