EP0107394A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: Fujitsu Ltd
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Filing: 1983-09-29
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Granted: —
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Expires: 2003-09-29
Abstract
Abstract A semiconductor memory device having flip-flops (16, 17) for latching N-bit address information. The flip-flops are provided in master-slave arrangements. N master flip-flops (16) are formed in an address input buffer (3) and 2 N slave flip-flops (17) are formed in word line driver circuits. A decoder (4) is formed between the master and slave flip-flops. The flip-flops are all internal to the IC of the memory device.
Inventors
- 👤 Kazuo Ooami
- 👤 Yasuhisa Sugo
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 21:23
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/10; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/414; G11C11/415; G11C8/06
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
62 words
A semiconductor memory device comprising first flip-flop circuits arranged for receiving address inputs; decoder circuits operatively connected to the first flip-flop circuits to decode the outputs thereof and to provide selection output signals, and second flip-flop circuits operatively connected to the decoder circuits to receive the outputs thereof, the first and second flip-flop circuits cooperating to form master slave flip-flop circuit arrangements.
Claim 2
Dependent Claim
62 words
A semiconductor memory device comprising first flip-flop circuits arranged for receiving address inputs; decoder circuits operatively connected to the first flip-flop circuits to decode the outputs thereof and to provide selection output signals, and second flip-flop circuits operatively connected to the decoder circuits to receive the outputs thereof, the first and second flip-flop circuits cooperating to form master slave flip-flop circuit arrangements.
Claim 3
Dependent Claim
25 words
A semiconductor memory device as claimed in claim 1, adapted to handle N-bit addresses, having N first flip-flop circuits and 2 N second flip-flop circuits.
Claim 4
Dependent Claim
32 words
A semiconductor memory device as claimed in claim 1 or 2,wherein the first flip-flop circuits and the second flip-flop circuits operate complementarily in response to a clock signal delivered to the device.
Claim 5
Dependent Claim
24 words
A semiconductor memory device as claimed in any preceding claim, having word lines arranged to be driven in dependence upon the selection output signals.
Claim 6
Dependent Claim
24 words
A semiconductor memory device as claimed in any preceding claim, having bit lines arranged to be driven in dependence upon the selection output signals.
Claim 7
Dependent Claim
40 words
A semiconductor memory device as claimed in any preceding claim, wherein the first flip-flop circuits are incorporated in an address input buffer of the device, and the second flip-flop circuits are incorporated in line driver circuits of the memory device.
Claim 8
Dependent Claim
29 words
A semiconductor memory device as claimed in any preceding claim, being an 1C memory device wherein the first and second flip-flop circuits are formed internally of the memory IC.
References Cited (Backward Citations)
No citation records indexed.
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