EP0115002A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Voltage transient protection circuit
Assignee: Motorola Solutions Inc
•
Filing: 1983-12-16
•
Granted: —
•
Expires: 2003-12-16
Abstract
Abstract A three terminal integrated low-resistant series switch circuit (10) which buffers load electronics from extreme input voltage conditions. The circuit comprises a series pass transistor (20) the conductivity of which is controlled by control circuitry (22, 24, 28, 32) in cooperation with feedback control (36). In response to the input exceeding a predetermined operating potential the series pass transistor is driven toward saturation and is maintained in this state by feedback whereby only that load current required by the load electronics is supplied for increased efficiency. The control circuitry is responsive to the signal at the input thereof exceeding a predetermined level for rendering the series pass transistor nonconducting to protect the load electronics from extreme voltage excursions. A feature of the circuit is that the epitaxial layer within which the control circuit is formed is operated at a lower voltage than that of the substrate.
Inventors
- 👤 Byron G. Bynum
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 13:48
CPC Classifications
H; H02; H02H; H02H7/00; H02H7/20
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
168 words
A monolithic integrated circuit comprising: a vertical structured PNP transistor having an emitter and collector coupled respectively to the input and output of the circuit and a base, said 4collector being formed by a portion of the substrate comprising the integrated circuit, said base being formed by a region of the epitaxial layer of the integrated circuit and said emitter being formed in a region of said epitaxial layer; control circuit means formed in said epitaxial layer which is responsive to an external signal applied to the input of the integrated circuit for controlling the conduction of said PNP transistor wherein said PNP transistor tends to be driven into saturation; and sense circuit means for sensing when said PNP transistor is driven into saturation for providing a feedback control signal to an input of said control circuit means to minimize the base current drive of said PNP transistor with respect to the collector current whereby said substrate is maintained at a more positive potential than said epitaxial layer.
Claim 2
Dependent Claim
168 words
A monolithic integrated circuit comprising: a vertical structured PNP transistor having an emitter and collector coupled respectively to the input and output of the circuit and a base, said 4collector being formed by a portion of the substrate comprising the integrated circuit, said base being formed by a region of the epitaxial layer of the integrated circuit and said emitter being formed in a region of said epitaxial layer; control circuit means formed in said epitaxial layer which is responsive to an external signal applied to the input of the integrated circuit for controlling the conduction of said PNP transistor wherein said PNP transistor tends to be driven into saturation; and sense circuit means for sensing when said PNP transistor is driven into saturation for providing a feedback control signal to an input of said control circuit means to minimize the base current drive of said PNP transistor with respect to the collector current whereby said substrate is maintained at a more positive potential than said epitaxial layer.
Claim 3
Dependent Claim
48 words
The circuit of claim 1 including protection circuit means coupled between the input of the circuit and said input of said control circuit means for providing a control signal thereto in response to said external signal exceeding a predetermined value such that said PNP transistor is rendered nonconductive.
Claim 4
Dependent Claim
55 words
The circuit of claim 2 including short circuit protection means coupled to said input of said control circuit means which is responsive to said collector current of said PNP transistor exceeding a predetermined value for providing a control signal to said control circuit means to regulate said collector current at substantially said predetermined value. --
Claim 5
Dependent Claim
36 words
The circuit of claim 2 or 3 wherein said sense circuit means comprises a region of semiconductor material of like conductivity as said emitter region of said PNP transistor in close proximity to said PNP transistor.
Claim 6
Dependent Claim
120 words
The circuit of claim 4 wherein said control circuit means: includes a first field effect transistor (FET) having a gate, source and drain electrodes, said source-drain electrodes being coupled in series between said base of said PNP transistor and a common terminal of the circuit; a first transistor of like conductivity type as said PNP transistor having an emitter coupled to the input of the circuit, a base, first and second collectors; latch circuit means coupled between said base and first collector of said first transistor to said common terminal for regulating the collector current sourced from said first collector; and first circuit means for coupling said second collector of said first transistor with said gate of said first FET.
Claim 7
Dependent Claim
46 words
The circuit of claim 5 wherein said control circuit means further includes a second FET having a source-to-drain path coupled in series between said gate of said first FET and said common terminal, the gate thereof being coupled to said input of said control circuit means.
Claim 8
Dependent Claim
57 words
The circuit of claim 6 wherein said protection circuit means includes: a second transistor having an emitter coupled to the input of the circuit, base and a collector, said base and collector being interconnected; and Zener diode means coupled between said interconnected base and collector of said second transistor and said input of said control circuit means.
Claim 9
Dependent Claim
48 words
The circuit of claim 7 wherein said short circuit protection means comprises a second collector region of said PNP transistor formed in lateral spaced relationship to said emitter and base of said PNP transistor, said second collector region being coupled to said input of said control circuit means.
Claim 10
Dependent Claim
93 words
The circuit of claim 8 wherein said latch circuit means includes: a third FET having a gate and a source-drain path coupled in series between said base of said first transistor and a common node; a fourth FET having a gate coupled to said first common node and a source-drain path coupled in series between said base of said first transistor and a common node; a fourth FET having a gate coupled to said first common node and a source-drain path coupled between said gate of said third FET and said common terminal:
Claim 11
Dependent Claim
25 words
The circuit of claim 9 wherein said second transistor of said protection circuit includes a second collector coupled to said base of said PNP transistor.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.