EP0118878A2
Expired / Lapsed
EP
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Semiconductor memory device
Assignee: Hitachi Ltd
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Filing: 1984-03-07
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Granted: —
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Expires: 2004-03-07
Abstract
Abstract In a semiconductor memory device including memory (7) and dummy cells (6) connected to groups of data lines (3), word lines (4) and dummy word lines (9) for selecting the memory and dummy cells, respectively, and a signal detector (8) for differentially amplifying the read signal from the memory cell selected by the signal of the word line and a reference signal from the dummy cell, the improvement wherein the memory cell capacitor (1) consists of two capacitors, each having substantially the same structure as a dummy cell capacitor (11) and connected in parallel with the other.
Inventors
- 👤 Katsutaka Kimura
- 👤 Ryoichi Hori
- 👤 Kiyoo Ito
- 👤 Hideo Sunami
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 09:09
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/24; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; G11C11/4063; G11C11/407; G11C11/409; G11C11/4099; H; H10; H10B; H10B12/00; H10B12/30; H10B12/37; H10D; H10D1/00; H10D1/60; H10D1/68
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
157 words
A semiconductor memory device comprising: a plurality of memory cells (7, 7n, 7n) connected to a plurality of data lines (3, 3n, 3n), respectively, and having first capacitors (1) for storing information; a plurality of dummy cells (6, 6n, 6n) connected to said data lines (3, 3n 3n), respectively, and having second capacitors (11) having the capacitance substantially the half of said first capacitors (1); and means (8) connected to selected first (3n) and second (3n) data lines of said data lines, for differentially detecting signals on said first and second data lines when one of said memory cells (7n) connected to said first data line (3n) is selected and one of said dummy cells (6n) connected to said second data line (3n) is selected; said first capacitor (1.; 5, .17) consisting of two capacitors (5, 17A; 5, 17B) connected in parallel with each other and having the same structure as said second capacitor (11; 5, 24).
Claim 2
Dependent Claim
157 words
A semiconductor memory device comprising: a plurality of memory cells (7, 7n, 7n) connected to a plurality of data lines (3, 3n, 3n), respectively, and having first capacitors (1) for storing information; a plurality of dummy cells (6, 6n, 6n) connected to said data lines (3, 3n 3n), respectively, and having second capacitors (11) having the capacitance substantially the half of said first capacitors (1); and means (8) connected to selected first (3n) and second (3n) data lines of said data lines, for differentially detecting signals on said first and second data lines when one of said memory cells (7n) connected to said first data line (3n) is selected and one of said dummy cells (6n) connected to said second data line (3n) is selected; said first capacitor (1.; 5, .17) consisting of two capacitors (5, 17A; 5, 17B) connected in parallel with each other and having the same structure as said second capacitor (11; 5, 24).
Claim 3
Dependent Claim
141 words
The semiconductor memory device as defined in claim 1 wherein said second capacitor (11) consists of a first groove portion (27) formed on a semiconductor substrate (19), a first insulating film (28;.29) formed on the surface of said groove portion (24) and a first capacitor electrode (5) laminated on said first insulating film, and defines an inversion layer (31) on the surface, and said first capacitor (1) consists of second (27A) and third (27B) groove portions juxtaposed with each other on said semiconductor substrate, second and third insulating films (28; 29) formed on the surfaces of said second and third groove portions (27A, 27B), respectively, and a common second capacitor electrode (5) disposed on said second and third insulating films, and defines inversion layers (31) connected conductively with each other, below the surfaces of said second and third groove portions, respectively.
Claim 4
Dependent Claim
96 words
The semiconductor memory device as defined in claim 2 wherein each of said memory cells consists of a field effect transistor (2) connecting said first capacitor (1) to the corresponding data line (3n, 3n), the gate of said transistor is connected to one corresponding word line (4, 4m, 4m), its source and drain are arranged in the extending direction of the corresponding data lines, and said second (27A) and third (27B) groove portions of each of said memory cells (7n, 7n) are juxtaposed in the direction crossing said data lines (3, 3n, 3n) at right angles.
Claim 5
Dependent Claim
45 words
The semiconductor memory device as defined in claim 2 wherein said second (27A) and third (27B) groove portions belonging to each of said first and second memory cells adjacent each other are juxtaposed in the same direction but at different positions in the same direction.
Claim 6
Dependent Claim
28 words
The semiconductor memory device as defined in claim 4 wherein said direction is one that is perpendicular to the extending directions of said data lines (3, 3n, 3n).
References Cited (Backward Citations)
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