Testing apparatus for redundant memory

Claim 2

In an apparatus for testing a redundant memory which applies a test pattern to a memory under test which is equipped with redundant lines, determines failures in said memory on the basis of test results obtained by comparing outputs from said memory under test with expected values, and remedies said failures by said redundant lines, the improvement comprising: (a) a compressed data matrix which compresses data on the test results into data necessary for an analysis of redundant line judgement, and stores said data therein; (b) an address conversion unit which converts the addresses of said failures into addresses of said compressed data matrix; and (c) an auxiliary processing unit which judges that remedy is possibility when the data on the test results is stored in said compressed data matrix, and determines a suitable redundant line; (d) said redundant line being determined by analyzing the data in said compressed data matrix.

Claim 3

The apparatus for testing a redundant memory as defined in claim 1 wherein the demensions x and y of the column and row sides of said compressed data matrix are represented by the following formulas, where N x and Ny are the numbers of redundant lines on the column and row sides, respectively:

Claim 4

The apparatus for testing a redundant memory as defined in claim 2 wherein said address conversion unit comprises: (a) a pair of failure line registers which hold the addresses on the column and row sides of the memory under test, respectively; (b) a pair of counters which receive outputs from said pair of failure line registers, respectively, count the number of new failure addresses generated, produce an output indicating whether or not the number of addresses of said compressed data matrix is within (z x y), and number the failure addresses in accordance with the sequence in which they occurred so that said addresses can be used as addresses of said compressed data matrix; (e) a pair of address registers which store said addresses obtained from said pair of counters so as to correspond to said failure addresses; and (f) a decoder which converts one of the address outputs from said pair of address registers as a data input to said compressed data matrix.

Claim 5

The apparatus for testing a redundant memory as defined in claim 3 wherein each of said failure line registers comprises a 1-bit wide RAM of a depth equal to the address length of said memory under test.

Claim 6

The apparatus for testing a redundant memory as defined in claim 3 wherein each of said auxiliary processing unit includes at least: (a) a pair of comparators which detect whether a new failure address obtained from said pair of counters is outside the dimensions (x x y) of said compressed data matrix; (b) a pair of line failure counters which decide on a redundant line of said memory under test, said counters deciding on said redundant line when it is detected that at least (N + 1) or (N + 1) failures are aligned on the same line of said memory under test; (c) a group of gates which receive outputs from said pair of line failure counters and outputs from said pair of comparators, and judge that said memory under test is "NG" when there is a failure outside the dimensions (X x y) of said compressed data matrix and said decision on a redundant line has not been made; and (d) gates provided in a stage before said line failure counters, which prevent double-counting when failures are detected at the same address.

Claim 7

The apparatus for testing a redundant memory as defined in claim 5 wherein said pair of line failure counters comprise N (or N ) RAMs that constitute said failure line registers.

Claim 8

The apparatus for testing a redundant memory as defined in claim 5 wherein redundant line counters for counting the number of redundant lines decided on are provided in an output stage of said line failure counters.

Claim 9

The apparatus for testing a redundant memory as defined in claim 5 which further includes remedy-decision line memories which store subsequent failure on the same line after said line failure counters have decided on a redundant line.

Claim 10

The apparatus for testing a redundant memory as defined in claim 8 wherein each of said remedy-decision line memories comprises N x line memories of the actual address length of the memory under test and N y line memories of the actual address length of said memory under test.

Claim 11

10 . The apparatus for testing a redundant memory as defined in claim 8 wherein one of said remedy-decision line memories is a memory consisting of-N x line memories on the column side, is formed-by extending said compressed data matrix on the row side, and which is of the actual address length of said memory under test.

Claim 12

The apparatus for testing a redundant memory as defined in claim 8 wherein one of said remedy-decision line memories is a memory formed by extending said compressed data matrix on the column side, consists of N y line memories on the row side, and which is of the actual address length of said memory being tested.

Claim 13

The apparatus for testing a redundant memory as defined in claim 8 wherein said remedy-decision line memory is a single memory formed by extending the widths on both column and row sides of said compressed data matrix to the actual address length of said memory being tested.