EP0127002A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
A method for maintaining the integrity of a dual microprocessor multiprocessing system and multiprocessing system
Assignee: Siemens AG
•
Filing: 1984-05-02
•
Granted: —
•
Expires: 2004-05-02
Abstract
Abstract A dual microprocessor computing system is used to control an engine in a motor vehicle. Each system contains a Personality Programmable Read Only Memory (PPROM) (44) containing system calibration data that is transferred from the PPROM to the read-write memories (84) in the microprocessors (26, 28). In order to identify each PPROM a byte of memory contains a check sum and a byte of the microprocessor memory contains an identical check sum. During data transfer, the check sums are compared. Also during data transfer, the amount of data being transferred within a predetermined interval is counted both at the transmitter and the receiver memories.
Inventors
- 👤 Michael A. Pauwels
- 👤 Danny Orlen Wright
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-25 05:36
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0751; G06F11/0754; G06F11/076; F; F02; F02D; F02D41/00; F02D41/24; F02D41/2406; F02D41/2425; F02D41/26; F02D41/266; F02P; F02P15/00; F02P15/008; G06F11/0706; G06F11/0721; G06F11/0724; G06F11/0763
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
112 words
A method for maintaining the integrity of a dual microprocessor multiprocessing computing. system comprising the steps of: initializing (116) the system for placing the system in a base line condition; addressing a programmable read only memory (44) for reading a check sum (l18) representing the total bit signals contained therein; comparing (119) the check sum (118) from the programmable read only memory (44) with a predetermined check sum (120) located in the first microprocessor to determine the compatability of the read only memory (44) and the first microprocessor (26); and then reinitializing (82) the system if the predetermined check sum is different (122) than the check sum from the read only memory.
Claim 2
Independent Claim
112 words
A method for maintaining the integrity of a dual microprocessor multiprocessing computing. system comprising the steps of: initializing (116) the system for placing the system in a base line condition; addressing a programmable read only memory (44) for reading a check sum (l18) representing the total bit signals contained therein; comparing (119) the check sum (118) from the programmable read only memory (44) with a predetermined check sum (120) located in the first microprocessor to determine the compatability of the read only memory (44) and the first microprocessor (26); and then reinitializing (82) the system if the predetermined check sum is different (122) than the check sum from the read only memory.
Claim 3
Independent Claim
116 words
A method for maintaining the integrity of a dual microprocessor multiprocessing computing system comprising the steps of: initiating (116) in response to an initializing signal, a timing period in a second microprocessor having a predetermined time length; transmitting (124) a predetermined number of bit signals from a read only memory through the first microprocessor (26) to the second microprocessor (28); counting (126) the number of bit signals being received in the second microprocessor (28) within said time period; comparing (128) the predetermined number with the count of the bit signals received in said time period; and then reinitializing (82) the system after the end of the timing period if the count and the number are unequal.
Claim 4
Independent Claim
116 words
A method for maintaining the integrity of a dual microprocessor multiprocessing computing system comprising the steps of: initiating (116) in response to an initializing signal, a timing period in a second microprocessor having a predetermined time length; transmitting (124) a predetermined number of bit signals from a read only memory through the first microprocessor (26) to the second microprocessor (28); counting (126) the number of bit signals being received in the second microprocessor (28) within said time period; comparing (128) the predetermined number with the count of the bit signals received in said time period; and then reinitializing (82) the system after the end of the timing period if the count and the number are unequal.
Claim 5
Independent Claim
104 words
A method for maintaining the integrity of a dual microprocessor multiprocessing computing system comprising the steps of: transmitting (124) bit signals from a read only memory through the first microprocessor to the second microprocessor; counting the bit signals being transmitted from the first microprocessor; counting (126) the bit signals being received by the second microprocessor; transmitting the count from the second microprocessor to the first microprocessor; comparing (128) in the first microprocessor the count of the bit signals transmitted with the count of the bit signals received; and then reinitializing (82) the system if the transmitted count is not equal to the received count.
Claim 6
Independent Claim
104 words
A method for maintaining the integrity of a dual microprocessor multiprocessing computing system comprising the steps of: transmitting (124) bit signals from a read only memory through the first microprocessor to the second microprocessor; counting the bit signals being transmitted from the first microprocessor; counting (126) the bit signals being received by the second microprocessor; transmitting the count from the second microprocessor to the first microprocessor; comparing (128) in the first microprocessor the count of the bit signals transmitted with the count of the bit signals received; and then reinitializing (82) the system if the transmitted count is not equal to the received count.
Claim 7
Dependent Claim
183 words
In a dual microprocessor multiprocessing computing system having a programmable read only memory (44) containing data for a particular application of the computing system, at least two microprocessors (26, 28) each having timer means (92) and a plurality of memories (84, 86), wherein the first one of the microprocessors (26) is the master microprocessor and operates to synchronize the second microprocessor (28) thereto, a watchdog system for maintaining the integrity of the computing system, said system comprising: means (116) for generating an intializing signal operable to reset the computing system to a base line condition; means (118) within the programmable read only memory for maintaining a first identifier for indicating the characteristics of the programmable read only memory; means (120) within the first microprocessor for maintaining a second identifier for indicating the correct programmable read only memory to connect to said fast microprocessor; comparison (119) means for comparing the first identifier with the second identifier; and means (124) responsive to said comparison means and operable when said identifiers are equivalent to initiate data transmission between the programmable read only memory and the microprocessors.
Claim 8
Dependent Claim
183 words
In a dual microprocessor multiprocessing computing system having a programmable read only memory (44) containing data for a particular application of the computing system, at least two microprocessors (26, 28) each having timer means (92) and a plurality of memories (84, 86), wherein the first one of the microprocessors (26) is the master microprocessor and operates to synchronize the second microprocessor (28) thereto, a watchdog system for maintaining the integrity of the computing system, said system comprising: means (116) for generating an intializing signal operable to reset the computing system to a base line condition; means (118) within the programmable read only memory for maintaining a first identifier for indicating the characteristics of the programmable read only memory; means (120) within the first microprocessor for maintaining a second identifier for indicating the correct programmable read only memory to connect to said fast microprocessor; comparison (119) means for comparing the first identifier with the second identifier; and means (124) responsive to said comparison means and operable when said identifiers are equivalent to initiate data transmission between the programmable read only memory and the microprocessors.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.