Planar interconnection for integrated circuits

Claim 2

A semiconductor device comprising: a semiconductor substrate having at least one semiconductor region; a layer of electrically insulating material located on a surface of said substrate, said layer having a substantially planar top surface; a layer of electrically conductive material recessed in said insulating layer, said conductive layer having a predetermined pattern with its top surface in the same plane as the top surface of said insulating layer; and at least one electrical contact located between a predetermined region of said conductive layer and a portion of said semiconductor region, said contact having a portion thereof located in a corresponding via in said insulating layer.

Claim 3

The semiconductor device of Claim 1 wherein said conductive layer and said contact are free of voids.

Claim 4

An integrated circuit comprising: a semiconductor substrate having at least one semiconductor device; a first layer of electrically insulating material located on a surface of said substrate, said layer having a substantially planar top surface; a first layer of electrically conductive material recessed in said first insulating layer, said first conductive layer having a first predetermined pattern with its top surface in the same plane as the top surface of said first insulating layer; at least one electrical contact located between a predetermined region of said first conductive layer and a semiconductor region of said device, said contact having a portion thereof located in a corresponding via in said first insulating layer; a second layer of insulating material overlying a composite planar surface provided by the top surfaces of said first insulating and conductive layers; a second layer of electrically conductive material recessed in said second insulating layer and substantially insulated from said first condcutive layer by said second insulating layer, said second conductive layer having a second predetermined pattern with its top surface in the same plane as the top surface of said second insulating layer and providing a second composite planar surface; and at least one electrical contact between a predetermined region of said second conductive layer and a corresponding region of said first conductive layer, said contact being formed in a corresponding via in said second insulating layer. The integrated circuit of Claim 3 wherein a plurality of semiconductor devices having semiconductor regions are located in said semiconductor substrate, a plurality of electrical contacts are located between said first layer of electrically conductive material and said regions of said semiconductor devices, and a plurality of electrical contacts are located between predetermined regions of said second layer of electrically conductive material and corresponding regions of said first layer of electrically conductive material.

Claim 5

The integrated circuit of Claim 3 wherein said first insulating layer comprises flowable material means for planarizing the composite surface.

Claim 6

The integrated circuit of Claim 3 wherein electrically conductive lines provided by said first pattern cross electrically conductive lines provided by said second pattern at any selectable angle.

Claim 7

The integrated circuit of Claim 3 wherein the minimum line width of said first and second conductive pattern is less than 2 micrometers.

Claim 8

The integrated circuit of Claim 3, wherein said first and second conductive layers and said electrical contacts thereto are free of voids.

Claim 9

The integrated circuit of Claim 3, further comprising at least one additional insulating layer disposed over said second conductive and insulating layer and having an additional electrically conductive layer in contact with said additional insulating layer, and a plurality of electrical contacts connecting said additional conductive layer to predetermined regions of said second conductive layer.

Claim 10

The integrated circuit of Claim 3 wherein at least one of said first and second conductive patterns comprises a metal.

Claim 11

The integrated circuit of Claim 3 wherein at least one of said first and second conductive patterns comprises a doped polysilicon material.

Claim 12

The integrated circuit of Claim 3 wherein one of said first and second conductive patterns comprises a conductive material other than metal.

Claim 13

An integrated circuit comprising: a substrate having a plurality of devices on its surface; a plurality of insulating layers disposed over said substrate; and a plurality of electrically conductive layers having predetermined patterns, each of said conductive layers being partially embedded in and supported by a corresponding insulating layer, the top surface of said conductive layer and corresponding insulating layer providing a substantially planar composite surface, each of said insulating layers having predetermined contact vias filled with conductive material for forming contacts interconnecting the selected regions of current layer to selected regions of a lower one, or, in the case of the first layer, to corresponding regions of said devices.

Claim 14

An integrated circuit comprising: a substrate having a plurality of devices on its surface; a plurality of insulating layers disposed over said substrate; and a plurality of electrically conductive layers having predetermined patterns, each of said conductive layers being partially embedded in and supported by a corresponding insulating layer, the top surface of said conductive layer and corresponding insulating layer providing a substantially planar composite surface, each of said insulating layers having predetermined contact vias filled with conductive material for forming contacts interconnecting the selected regions of current layer to selected regions of a lower one, or, in the case of the first layer, to corresponding regions of said devices.

Claim 15

The integrated circuit of Claim 13 wherein at least one region of at least one of said conductive layers forms a contact pad from the current layer to a contact in an upper layer.

Claim 18

The method of Claim 15 further comprising the steps of repeating steps 2 through 7 until a selected number of conductive layers has been formed.

Claim 19

The method of Claim 15 wherein the step of providing the first portion of the first insulating layer comprises the flowing of a glassy material to planarize the top surface thereof.

Claim 20

The method of Claim 15 wherein the steps of providing a solid conductive contact filler material and of providing a conductive pattern filler material each comprises the further steps of: depositing a conductive layer over the corresponding opened insulating layer portion; providing a mask for said conductive layer; selectively etching the conductive layer in a direction perpendicular to the plane of the substrate until those portions of the conductive layer not masked are removed; and removing the mask.

Claim 21

The method of Claim 18 wherein said selective etching step comprises the reactive ion etching of the conductive layer with an anisotropic etchant to preferentially etch away portions of said conductive layer.

Claim 22

The method of Claim 19 wherein said reactive ion etching step uses a gaseous anisotropic etchant to provide a selectivity for etching the conductive layer substantially greater than for the insulating layer.

Claim 25

The method of Claim 21 wherein said anisotropic and selective etching steps comprise reactive ion etching with a gas mixture selected to provide substantial directivity in a direction perpendicular to the substrate surface and an etch rate for the material to be etched substantially greater than.the etch rate for the other material exposed to the etchant.