EP0130798A2
Expired / Lapsed
EP
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Semiconductor memory device
Assignee: Fujitsu Ltd
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Filing: 1984-06-28
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Granted: —
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Expires: 2004-06-28
Abstract
Abstract In a semiconductor memory device including word lines (WL) and bit lines (BL), a regular circuit area comprising elements regularly arranged in line with the word lines and/or the bit lines is divided into a plurality of blocks (1-1, 1-2). Provided between the divided blocks are irregular or peripheral circuit areas (2). Provided outside of the divided blocks are pads (P<sub>1</sub> to P<sub>16</sub>).
Inventors
- 👤 Yoshihiro Takemae
- 👤 Tomio Nakano
- 👤 Kimiaki Sato
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 09:02
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/90; G; G11; G11C; G11C5/00; G11C5/02; G11C5/025; G11C5/14; H10W72/071; H10W72/075; H10W72/50; H10W72/541; H10W72/5449; H10W72/931; H10W72/932; H10W72/951; H10W72/952; H10W90/00; H10W90/701; H10W90/751; H10W90/756
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
53 words
A semiconductor memory chip having a plurality of regularly arrayed memory cells, and also having auxiliary circuitry, arranged adjacent to the arrayed memory cells,for use in operating the memory cells, characterised in that the said auxiliary circuitry is located on an area of the chip between two separate arrays of the memory cells.
Claim 2
Dependent Claim
53 words
A semiconductor memory chip having a plurality of regularly arrayed memory cells, and also having auxiliary circuitry, arranged adjacent to the arrayed memory cells,for use in operating the memory cells, characterised in that the said auxiliary circuitry is located on an area of the chip between two separate arrays of the memory cells.
Claim 3
Dependent Claim
88 words
A semiconductor memory device comprising: a plurality of word lines (WL); a plurality of bit lines (BL); at least two separated regular circuit area means (1-1, 1-2) each comprising elements arranged regularly in line with said word lines or said bit lines; irregular circuit area means (2) arranged between said separated regular circuits, each of said irregular circuit areas comprising elements irregularly arranged regarding said word lines and said bit lines; and bonding pad areas (P 1 to P 16 ) arranged on the periphery of said device.
Claim 4
Dependent Claim
88 words
A semiconductor memory device comprising: a plurality of word lines (WL); a plurality of bit lines (BL); at least two separated regular circuit area means (1-1, 1-2) each comprising elements arranged regularly in line with said word lines or said bit lines; irregular circuit area means (2) arranged between said separated regular circuits, each of said irregular circuit areas comprising elements irregularly arranged regarding said word lines and said bit lines; and bonding pad areas (P 1 to P 16 ) arranged on the periphery of said device.
Claim 5
Dependent Claim
31 words
A device as set forth in claim 2 , wherein said bonding pad areas comprise pads arranged outside of said separated regular circuit area means on the periphery of said device.
Claim 6
Dependent Claim
42 words
A device as set forth in claim 3, wherein said bonding pad areas further comprise pads (P' 4 , P' 5 , P' 12 , P' 13 ) arranged outside of said irregular circuit area means on the periphery of said device.
Claim 7
Dependent Claim
66 words
5 . A device as set forth in claim 4 , wherein said pads (P' 4 , P' 5 , P' 12 , P' 13 ) arranged outside of said peripheral circuit area means have the same purpose as the corresponding ones (P 4 , P 5 , P 12 , P 13 ) of said pads arranged outside of said separated regular circuit area means.
Claim 8
Dependent Claim
30 words
A device as set forth in claim 5, further comprising an electrical means for connecting said pads (P 13 , P' 13 ) having the same purpose to each other.
Claim 9
Dependent Claim
29 words
A device as set forth in claim 6 , wherein said electrically connecting means comprises connections (Fig. 5A) for connecting said pads having the same purpose to each other.
Claim 10
Dependent Claim
48 words
A device as set forth in claim 6, wherein said electrically connecting means comprises a plurality of gates (G 1 , G 2 ) connected in parallel, each of said gates being connected to one of said pads (P 13' P ' 13 ) having the same purpose.
Claim 11
Dependent Claim
46 words
A device as set forth in claim 8, further comprising a means (G 3 , G 4 , G' 3 , G' 4 ), each connected to one of said pads having the same purpose, for preventing the potential thereof from being in a floating state.
Claim 12
Dependent Claim
54 words
A device as set forth in claim 9, further, comprising a means (G 5 , G 6 , G 7 ), connected to said preventing means (G' 3 , G' 4 ) for said pads (P 13 , P' 13 ) having the same purpose, for selecting and operating one of said preventing means.
References Cited (Backward Citations)
No citation records indexed.
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