EP0132988A2
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Digital synthesis technique for pulses having predetermined time and frequency domain characteristics
Assignee: AT&T Inc
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Filing: 1984-07-18
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Granted: —
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Expires: 2004-07-18
Abstract
Abstract A digital synthesis technique provides pulse shaping in accordance with predetermined time domain and frequency domain constraints. In the technique, the informational content of a binary bit stream is used by an access circuit (12) to form address words for accessing a read-only-memory (13). The digital representations stored in the ROM (13) represent a superposition of temporally-displaced truncated impulse time functions, each weighted by the discrete transmission symbol levels of the analog output signal. The digital representations from two ROMs (13-1 and 13-2) are toggled by a sequencing circuit. In other embodiments of the invention, different memory arrangements ranging from a single ROM (142) to an array of ROMS (163-1 through 163-3 and 164-1 through 164-3) are respectively used to decrease circuit complexity. In a digital radio transmission application of the technique, this arrangement is economical, readily reproducible and stable since it obviates the need for conventional complex analog filters.
Inventors
- 👤 Walter Debus, Jr.
- 👤 Thomas Lawrence Osborne
- 👤 Curtis A. Siller, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 19:15
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/497
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
167 words
Apparatus for synthesizing a precisely controlled waveform with predetermined time domain and frequency domain characteristics in response to a binary input data stream, said waveform defined in terms of nominal discrete amplitude states wherein each discrete transmission amplitude state corresponds to a group of prearranged input binary bits, CHARACTERISED BY accessing means (12) for converting a prescribed portion of the binary input data sequence including a plurality of groups to at least one address; memory means (13) for producing at least two digital representations for each address, the digital representations corresponding to a composite formed by individual and identical impulse time functions temporally displaced one from another, each impulse function weighted in accordance with its respective discrete transmission level, the sequence of signaling interval spaced levels defined by the memory address: sequencing means (14) for producing the digital representations in predetermined successive time intervals; and converting means (16) for converting said digital representations to corresponding analog transmission levels having the predetermined time domain and frequency domain characteristics.
Claim 2
Dependent Claim
167 words
Apparatus for synthesizing a precisely controlled waveform with predetermined time domain and frequency domain characteristics in response to a binary input data stream, said waveform defined in terms of nominal discrete amplitude states wherein each discrete transmission amplitude state corresponds to a group of prearranged input binary bits, CHARACTERISED BY accessing means (12) for converting a prescribed portion of the binary input data sequence including a plurality of groups to at least one address; memory means (13) for producing at least two digital representations for each address, the digital representations corresponding to a composite formed by individual and identical impulse time functions temporally displaced one from another, each impulse function weighted in accordance with its respective discrete transmission level, the sequence of signaling interval spaced levels defined by the memory address: sequencing means (14) for producing the digital representations in predetermined successive time intervals; and converting means (16) for converting said digital representations to corresponding analog transmission levels having the predetermined time domain and frequency domain characteristics.
Claim 3
Dependent Claim
49 words
Apparatus according to claim 1 wherein the binary input data is indicative of a random sequence of independent discrete amplitude levels and said accessing means (12) comprises a plurality of delaying means (22,23) for producing a parallel binary address from selected serial bits in the binary input data stream.
Claim 4
Dependent Claim
103 words
Apparatus according to claim 1 wherein said accessing means (12) produces the parallel binary address including a predetermined sequence of successive groups, wherein one element of the sequence of groups is indicative of the present group, one end of the sequence of groups is indicative of past groups and the other end of the sequence of groups is indicative of future groups so that the net response is a composite made up of all groups, each weighted in accordance with a predetermined temporally-displaced impulse response, the temporal displacement corresponding to the temporal relationship of each individual group making up the sequence of groups.
Claim 5
Dependent Claim
91 words
Apparatus according to claim 2 wherein the accessing means. (12) further comprises a serial-to-parallel converter (21) connected so as to receive the binary input data stream and thus produce a plurality of output parallel data streams (A,B), a plurality of delaying means (22,23), each connected to one of the plurality of output parallel data streams (A,B) for producing a plurality of concurrent bits constituting the address, and busing means disposed between the plurality of the delaying means and the memory means (13) for producing at least one parallel binary address word.
Claim 6
Dependent Claim
44 words
Apparatus according to claim 3 wherein the memory means (13) comprises a plurality of individual memories (13-1,13-2) each addressed by at least a portion of one of the parallel binary addresses, each individual memory (13-1,13-2) storing at least a portion of the digital representation.
Claim 7
Dependent Claim
40 words
Apparatus according to claim 5 wherein the plurality of individual memory means (13-1,13-2) comprises two memories, one memory' (13-1) storing one of the two digital signal representations and the other memory (13-2) storing the other of two digital signal representations.
Claim 8
Dependent Claim
74 words
Apparatus according to claim 6 wherein each of the two memories (13-1,13-2) is further divided into a plurality of divisional memories (163-4 to 163-3, 164-1 to 164-3) wherein each divisional memory receives a portion of the binary address and stores an additive part of the digital signal representations corresponding to a combination of respective portions, so that collectively each plurality of divisional memories provides a single output which is a complete digital signal representation.
Claim 9
Dependent Claim
61 words
Apparatus according to claim 6 wherein the sequencing means (14) comprises input means (24-1 to 24-16) for storing the digital representations from the two memories for the duration of the signaling interval, and output means (26-1 to 26-16) for obtaining one digital representation from the input means and then the other digital representation from the input means during each signaling interval.
References Cited (Backward Citations)
No citation records indexed.
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