EP0136170A2
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A semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1984-09-25
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Granted: —
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Expires: 2004-09-25
Abstract
Abstract 57 A semiconductor memory device in which the differential amplifier circuit compares a potential of a bit line to which memory cells storing information are connected with a reference potential of a dummy line to which a dummy cell is connected, and detects information stored in each of the memory cells. The semiconductor memory device comprises a circuit which discharges both the bit line and the dummy line to a low potential when the chip enable inverted signal is supplied. When the chip enable signal is supplied, therefore, the differential amplifier circuit can detect a difference between the bit line potential and the dummy line potential before the bit line is fully charged up. This makes it possible to produce the chip enable access time and to realize higher speed operations.
Inventors
- 👤 Sumio Tanaka
- 👤 Shinji 507 Koyo-Ofuna-Mansion Saito
- 👤 Shigeru Atsumi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 11:02
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/14; G11C7/06; G11C7/062; G11C7/12; G11C8/00; G11C8/18
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
122 words
1 . A semiconductor memory device which comprises: memory cells storing information; a bit line connected to said memory cells; differential amplifier means having a first input terminal at which the potential of said bit line is fed as input and a second input terminal at which a reference potential is fed as input, said differential amplifier means comparing these two potentials fed at said first and second input terminals with each other and detecting information stored in each of said memory cells; first means for discharging said bit line to a predetermined potential when a chip enable inverted signal is supplied; and second means for discharging said reference potential to a predetermined level when the chip enable inverted signal is supplied.
Claim 2
Dependent Claim
122 words
1 . A semiconductor memory device which comprises: memory cells storing information; a bit line connected to said memory cells; differential amplifier means having a first input terminal at which the potential of said bit line is fed as input and a second input terminal at which a reference potential is fed as input, said differential amplifier means comparing these two potentials fed at said first and second input terminals with each other and detecting information stored in each of said memory cells; first means for discharging said bit line to a predetermined potential when a chip enable inverted signal is supplied; and second means for discharging said reference potential to a predetermined level when the chip enable inverted signal is supplied.
Claim 3
Dependent Claim
88 words
A semiconductor memory device as claimed in Claim 1, in which said first means is an n-channel. FET whose drain is connected to said first input terminal of said differential amplifier means, whose source is grounded, and whose gate is supplied as input with the chip enable inverted signal and said second means is an n-channel FET whose drain is connected to said second input terminal of said differential amplifier means, whose source is grounded, and whose gate is supplied as input with the chip enable inverted signal.
Claim 4
Dependent Claim
98 words
A semiconductor memory device as claimed in Claim 2, in which said differential amplifier means further comprises: first and second n-channel FETs whose gates are connected to said first and second input terminals respectively and whose sources are connected with each other; first and second p-channel FETs whose drains are connected to the drains of said first and second n-channel FETs respectively, whose gates are both connected to the drain of said second n-channel FET, and whose sources are both connected to a power supply; and an output terminal connected to the drain of said first n-channel FET.
Claim 5
Dependent Claim
127 words
A semiconductor memory device which comprises: memory cells storing information; a bit line connected to said memory cells; a dummy cell storing dummy information; a dummy line connected to said dummy cell; differential amplifier means having a first input terminal at which said bit line is connected and a second input terminal at which said dummy line is connected, said differential amplifier means comparing these two potentials fed at said first and second input terminals with each other and detecting information stored in each of said memory cells; first means for discharging said bit line to a predetermined potential when a chip enable inverted signal is supplied; and second means for discharging said dummy line to a predetermined potential when the chip enable inverted signal is supplied.
Claim 6
Dependent Claim
127 words
A semiconductor memory device which comprises: memory cells storing information; a bit line connected to said memory cells; a dummy cell storing dummy information; a dummy line connected to said dummy cell; differential amplifier means having a first input terminal at which said bit line is connected and a second input terminal at which said dummy line is connected, said differential amplifier means comparing these two potentials fed at said first and second input terminals with each other and detecting information stored in each of said memory cells; first means for discharging said bit line to a predetermined potential when a chip enable inverted signal is supplied; and second means for discharging said dummy line to a predetermined potential when the chip enable inverted signal is supplied.
Claim 7
Dependent Claim
88 words
A semiconductor memory device as claimed in Claim 4, in which said first means is an n-channel FET whose drain is connected to said first input terminal of said differential amplifier means, whose source is grounded, and whose gate is supplied as input with the chip enable inverted signal and said second means is an n-channel FET whose drain is connected to said second input terminal of said differential amplifier means, whose source is grounded, and whose gate is supplied as input with the chip enable inverted signal.
Claim 8
Dependent Claim
98 words
A semiconductor memory device as claimed in Claim 5, in which said differential amplifier means further comprises: first and second n-channel FETs whose gates are connected to said first and second input terminals respectively and whose sources are connected with each other; first and second p-channel FETs whose drains are connected to the drains of said first and second n-channel FETs respectively, whose gates are both connected to the drain of said second n-channel FET, and whose sources are both connected to a power supply; and an output terminal connected to the drain of said first n-channel FET.
Claim 9
Dependent Claim
79 words
A semiconductor memory device as claimed in Claim 5, which further comprises: first and second intrinsic n-channel FETs whose sources are connected to said first and second input terminals respectively and whose gates are supplied with the power supply; and first and second p-channel FETs whose drains are connected to said first and second intrinsic n-channel FETs respectively, whose gates are supplied as input with the chip enable inverted signal, and whose sources are supplied with the power supply.
Claim 10
Dependent Claim
79 words
A semiconductor memory device as claimed in Claim 5, which further comprises: first and second p-channel FETs whose drains are connected to said first and second input terminals respectively and whose gates and drains are connected to each other respectively; and first and second p-channel FETs whose drains are connected to said first and second p-channel FETs, whose gates are supplied as input with the chip enable inverted signal, and whose sources are both supplied with the power supply.
Claim 11
Dependent Claim
91 words
A semiconductor memory device as claimed in Claim 5, which further comprises: a first bias circuit inserted between the first input terminal of said differential amplifier means and said bit line, said first bias circuit biasing the potential of said bit line so that said potential assumes either of predetermined values; and a second bias circuit inserted between said second input terminal of said differential amplifier means and said dummy line, said second bias circuit biasing the potential of said dummy line so that said potential assumes either of predetermined values.
Claim 12
Dependent Claim
91 words
A semiconductor memory device as claimed in Claim 6, which further comprises: a first bias circuit inserted between the first input terminal of said differential amplifier means and said bit line, said first bias circuit biasing the potential of said bit line so that said potential assumes either of predetermined values; and a second bias circuit inserted between said second input terminal of said differential amplifier means and said dummy line, said second bias circuit biasing the potential to said dummy line so that said potential assumes either of predetermined values.
References Cited (Backward Citations)
No citation records indexed.
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