EP0136207A1
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EP
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Test period generator for automatic test equipment
Assignee: Fairchild Semiconductor Corp
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Filing: 1984-08-01
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Granted: —
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Expires: 2004-08-01
Abstract
Abstract A timing subsystem 10 including several test period generators for supplying a variety of timing signals to a device under test. Major, minor, and free-run period generators each supply various timing signals to a multiplexer 18, which selectively connects the timing signals to timing generators 20. A central processing unit 28 supplies data to the period generators and timing generators to define their respective timing signals. Timing signals generated by the major period generator 12 define the overall testing rate. The minor period generator 14 generates multiple timing signals within the periods of the major clock signals to permit higher clock rates. Timing signals that are independent of the major clock periods are generated by the free-run period generator 16. An external synchronizer circuit 26 provides a feedback loop from the device under test 22 to the major period generator. A reference driver trigger delay circuit 27 provides means for calibrating the timing generators. Each of the three period generators includes two interconnected timing interval generators 30 and 40 that alternately generate overlapping timing signals. Each timing interval generator includes a stop-restart oscillator 32, a counter 34, and a delay-line vernier 36. Upon the receipt of a start signal, the oscillator stops and restarts to align its clock pulses to the start signal. The oscillator output clocks the counter, which supplies a signal to the vernier when a preselected number is reached. The vernier delays the counter signal by a preselected delay and issus a signal that designates the end of the period.
Inventors
- 👤 Burnell G. West
- 👤 Richard F. Herlein
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 13:25
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/3193; G01R31/31935; G01R31/31712; G01R31/31713; G01R31/31903; G01R31/31908; G01R31/3191; G01R31/31917; G01R31/31922; G01R31/31924; G01R31/31928; G01R31/31937; G11; G11C; G11C7/00; G11C7/22; H; H03; H03K; H03K5/00; H03K5/13; H03K5/131; H03K5/14; G01R31/31926; H03K2005/00013; H03K2005/0015; H03K2005/00234; H03K2005/00247; H03K2005/00254; H03K2005/0026
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
212 words
A timing device for generating timing signals having selected time intervals and for supplying said timing signals to a timing generator device, said timing device characterized by: a major period generator for generating a first set of timing signals, said first set of timing signals including a major time zero signal that indicates the boundaries of major test periods and also including a major clock signal, wherein said major clock signal is aligned with respect to the beginning of each major test period, and wherein the duration of each of said major test periods is selectable; a minor period generator coupled to said major period generator for generating a second set of timing signals, said second set of timing signals including a minor time zero signal that indicates the boundaries of minor test periods and also including a minor clock signal, wherein said minor clock signal is aligned with respect to the beginning of each minor test period, and wherein all of said minor test periods within a major test period are equal to a selected duration and are aligned with respect to the beginning of a major test period; and signal selection means coupled to said major and minor period generators for supplying selected timing signals to said timing generator device.
Claim 2
Dependent Claim
212 words
A timing device for generating timing signals having selected time intervals and for supplying said timing signals to a timing generator device, said timing device characterized by: a major period generator for generating a first set of timing signals, said first set of timing signals including a major time zero signal that indicates the boundaries of major test periods and also including a major clock signal, wherein said major clock signal is aligned with respect to the beginning of each major test period, and wherein the duration of each of said major test periods is selectable; a minor period generator coupled to said major period generator for generating a second set of timing signals, said second set of timing signals including a minor time zero signal that indicates the boundaries of minor test periods and also including a minor clock signal, wherein said minor clock signal is aligned with respect to the beginning of each minor test period, and wherein all of said minor test periods within a major test period are equal to a selected duration and are aligned with respect to the beginning of a major test period; and signal selection means coupled to said major and minor period generators for supplying selected timing signals to said timing generator device.
Claim 3
Dependent Claim
46 words
A timing device as recited in claim 1 characterized in that said major period generator has first and second timing interval generators, said first and second timing interval generators are interconnected and each generates said major time zero and clock signals for alternate major test periods.
Claim 4
Dependent Claim
46 words
A timing device as recited in claim 2 characterized in that said minor period generator has third and fourth timing interval generators, said third and fourth timing interval generators are interconnected and each generates said minor time zero and clock signals for alternate minor test periods.
Claim 5
Dependent Claim
45 words
A timing device as recited in claim 1, 2 or 3 characterized in that said signal selection means comprises a multiplexer coupled to receive said timing signals from said major and minor period generators and to supply selected timing signals to said timing generator device.
Claim 6
Dependent Claim
76 words
A timing device as recited in any one of claims 1-4 characterized by a free-run period generator for generating a third set of timing signals, said third set of timing signals including a free-run time zero signal that indicates the boundaries of free-run periods and also including a free-run clock signal, wherein said free-run clock signal is aligned with respect to the beginning of each free-run period, wherein the duration of said free-run periods is selectable.
Claim 7
Dependent Claim
45 words
A timing device as recited in claim 5 characterized in that said free-run period generator has fifth and sixth timing interval generators, said fifth and sixth timing interval generators are interconnected and each generates said free-run time zero and clock signals for alternate free-run periods.
Claim 8
Dependent Claim
61 words
A timing device as recited in any one of claims 1-6 characterized by an external synchronizing and delay circuit for triggering said major period generator, said external synchronizing and delay circuit including a seventh timing interval generator that is operable for receiving an external trigger signal and, after a selected delay, for supplying a start signal to said major period generator.
Claim 9
Dependent Claim
291 words
A period generator circuit for generating timing signals, said circuit characterized by: a first timing interval generator for defining first phase test periods by supplying a first time zero signal, a first clock signal, and a first transfer signal, said first time zero signal is generated a fixed time after the receipt of a first trigger signal and defines the beginning of each of said first phase test periods, said first clock signal has a constant frequency and is aligned with respect to the beginning of each of said first phase test periods, said first transfer signal is delayed by a selected amount after the beginning of each of said first phase test periods; a second timing interval generator for defining second phase test periods by supplying a second time zero signal, a second clock signal, and a second transfer signal, said second time zero signal is generated a fixed time after the receipt of a second trigger signal and defines the beginning of each of said second phase test periods, said second clock signal has a constant frequency and is aligned with respect to the beginning of each of said second phase test periods, said second transfer signal is delayed by a selected amount after the beginning of each of said second phase test periods; and triggering means coupled to said first and second timing interval generators for alternately generating said first and second trigger signals, said triggering means is operable for generating the initial first trigger signal in response to the receipt of an external start signal, and is operable for thereafter alternately generating said second trigger signal upon the receipt of said first transfer signal and said first trigger signal upon the receipt of said second transfer signal.
Claim 10
Dependent Claim
291 words
A period generator circuit for generating timing signals, said circuit characterized by: a first timing interval generator for defining first phase test periods by supplying a first time zero signal, a first clock signal, and a first transfer signal, said first time zero signal is generated a fixed time after the receipt of a first trigger signal and defines the beginning of each of said first phase test periods, said first clock signal has a constant frequency and is aligned with respect to the beginning of each of said first phase test periods, said first transfer signal is delayed by a selected amount after the beginning of each of said first phase test periods; a second timing interval generator for defining second phase test periods by supplying a second time zero signal, a second clock signal, and a second transfer signal, said second time zero signal is generated a fixed time after the receipt of a second trigger signal and defines the beginning of each of said second phase test periods, said second clock signal has a constant frequency and is aligned with respect to the beginning of each of said second phase test periods, said second transfer signal is delayed by a selected amount after the beginning of each of said second phase test periods; and triggering means coupled to said first and second timing interval generators for alternately generating said first and second trigger signals, said triggering means is operable for generating the initial first trigger signal in response to the receipt of an external start signal, and is operable for thereafter alternately generating said second trigger signal upon the receipt of said first transfer signal and said first trigger signal upon the receipt of said second transfer signal.
Claim 11
Dependent Claim
75 words
A circuit as recited in claim 8 characterized in that said first and second timing interval generators respectively include first and second stop-restart oscillators for generating and aligning said first and second clock signals, respectively, and wherein said first stop-restart oscillator is stopped and restarted at the beginning of each of said first phase test periods, said second stop-restart oscillator is stopped and restarted at the beginning of each of said second phase test periods.
Claim 12
Dependent Claim
144 words
A circuit as recited in claim 9 characterized in that said first timing interval generator further includes a first counter that is clocked by said first clock signal and a first delay vernier coupled to the output of said first counter for generating said first transfer signal, and wherein said first transfer signal is generated after said first counter counts down to zero from a preselected number and after a preselected delay through said delay vernier; and wherein said second timing interval generator further includes a second counter that is clocked by said second clock signal and a second delay vernier coupled to the output of said second counter for generating said second transfer signal, and wherein said second transfer signal is generated after said second counter counts down to zero from a preselected number and after a preselected delay through said delay vernier.
Claim 13
Dependent Claim
117 words
A circuit as recited in claim 9 or 10 characterized in that said trigger means comprises first and second flip-flops respectively coupled to said first and second timing interval generators, said first flip-flop having a non-inverting output terminal coupled to restart said first oscillator, and having a clock input terminal coupled to receive said second transfer signal, an inverting output terminal of said first flip-flop being operable for generating said first time zero signal, said second flip-flop having a non-inverting output terminal coupled to restart said second oscillator,.and having a clock input terminal coupled to receive said first transfer signal, an inverting output terminal of said second flip-flop being operable for generating said second time zero signal.
Claim 14
Dependent Claim
62 words
A circuit as recited in claim 11 characterized in that said first time zero signal is generated by delaying a signal from said inverting output terminal of said first flip-flop through a first delay line, and wherein said second time zero signal is generated by delaying a signal from said inverting output terminal of said second flip-flop through a second delay line.
Claim 15
Dependent Claim
40 words
A circuit as recited in claim 12 characterized in that the delay of said first delay line is adjustable in duration and is selected so as to balance the total propagation delays of said first and second timing interval generators.
Claim 16
Dependent Claim
148 words
A timing device for calibrating first and second timing generators, said timing generators respectively operable for receiving first and second time-zero and clock signals and for generating first and second timing signals after first and second delays subsequent to the receipt of said first and second time-zero signals, said timing device characterized by: first means for generating a first time-zero signal and a first clock signal; programmable delay means, coupled to receive said first time-zero and clock signals, for generating a delayed sync signal after a programmable delay subsequent to the receipt of said first time-zero signal; second means for generating a second time-zero signal and a second clock signal a fixed delay after the receipt of said delayed sync signal, wherein the difference between said first delay and the sum of said programmable delay, said fixed delay, and said second delay is a measure of calibration error.
Claim 17
Dependent Claim
148 words
A timing device for calibrating first and second timing generators, said timing generators respectively operable for receiving first and second time-zero and clock signals and for generating first and second timing signals after first and second delays subsequent to the receipt of said first and second time-zero signals, said timing device characterized by: first means for generating a first time-zero signal and a first clock signal; programmable delay means, coupled to receive said first time-zero and clock signals, for generating a delayed sync signal after a programmable delay subsequent to the receipt of said first time-zero signal; second means for generating a second time-zero signal and a second clock signal a fixed delay after the receipt of said delayed sync signal, wherein the difference between said first delay and the sum of said programmable delay, said fixed delay, and said second delay is a measure of calibration error.
Claim 18
Dependent Claim
82 words
A timing device as recited in claim 14 characterized in that said programmable delay means comprises a counter disposed to receive said first clock signal, a vernier coupled to said counter and operable for supplying said delayed sync signal, a delay memory coupled to said counter and said vernier and containing a plurality of entries each specifying a programmable delay, and memory addressing means coupled to said delay memory for selecting a programmable delay by addressing one of said plurality of entries.
Claim 19
Dependent Claim
30 words
A timing device as recited in claim 15 characterized in that said memory addressing means comprises a counter operable for addressing successive entries at successive cycles of said timing device.
Claim 20
Dependent Claim
34 words
A timing device as recited in claim 14, 15 or 16 characterized in that said first means includes a stop-restart oscillator for aligning said first clock signal with respect to said first time-zero signal.
Claim 21
Dependent Claim
34 words
A timing device as recited in any one of claims 14-17 characterized in that said second means includes a stop-restart oscillator for aligning said second clock signal with respect to said second time-zero signal.
References Cited (Backward Citations)
No citation records indexed.
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