EP0141357A2
Expired / Lapsed
EP
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Monitor circuit
Assignee: Honeywell Inc
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Filing: 1984-10-20
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Granted: —
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Expires: 2004-10-20
Abstract
Abstract A circuit (10) for monitoring digital electrical signals which counts events (40), compares the event count to a threshold value (44), generates an equal value signal (50) when the threshold is attained and indicates the time elapsed (59) between an initial value (62) and the generation of the equal value signal (50). The event counter (12) is automatically cleared (18) or reset upon a user enabled automatic clear logic enabling signal (58). The circuit is preferably configured as a chip employing GaAs Schottky diode field effect transistor logic (SDFL) gates.
Inventors
- 👤 Devesh Bhatt
- 👤 Michael O. Schroeder
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 10:53
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/30; G06F11/34; G06F11/3466; G06F11/348; G06F11/3409; G06F11/3419; G06F2201/00; G06F2201/805; G06F2201/81; G06F2201/86; G06F2201/88
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
199 words
An electrical circuit for monitoring a monitored device which can be adapted to effect a digital electrical signal, wherein the occurrence of a selected event in said monitored device generates an event digital signal (32) and wherein a control device generates a digital clock signal, characterized by : a) first means (12) for counting said event digital signals so that the current value of said first counting means is an event count; b) means (14) for holding a threshold value; c) means (16) for comparing said threshold value to said event count and for generating an equal value digital signal (line 50) when said event count equals said threshold value; d) second means (20) for counting said digital clock signals so that the current value of said second counting means is a timing signal; e) means (line 62) for initializing said second counting means (20) to an initial value when said first counting means (12) is at a reference value; f) means (24) for recording said timing signal in response to a record signal (line 68); and g) means (18) for enabling the resetting of said event count to said reference value upon the occurrence of said record signal.
Claim 2
Dependent Claim
199 words
An electrical circuit for monitoring a monitored device which can be adapted to effect a digital electrical signal, wherein the occurrence of a selected event in said monitored device generates an event digital signal (32) and wherein a control device generates a digital clock signal, characterized by : a) first means (12) for counting said event digital signals so that the current value of said first counting means is an event count; b) means (14) for holding a threshold value; c) means (16) for comparing said threshold value to said event count and for generating an equal value digital signal (line 50) when said event count equals said threshold value; d) second means (20) for counting said digital clock signals so that the current value of said second counting means is a timing signal; e) means (line 62) for initializing said second counting means (20) to an initial value when said first counting means (12) is at a reference value; f) means (24) for recording said timing signal in response to a record signal (line 68); and g) means (18) for enabling the resetting of said event count to said reference value upon the occurrence of said record signal.
Claim 3
Dependent Claim
22 words
A circuit according to claim 1, characterized in that said record signal (line 68) is said equal value digital signal (line 50).
Claim 4
Dependent Claim
23 words
A circuit according to claim 1 or 2, characterized in that said initial value (line 62) and said reference value are each zero.
References Cited (Backward Citations)
No citation records indexed.
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