Electronic circuit capable of carrying out a succession of divisions at a high speed without an objectionable error

Claim 2

An electronic circuit for dividing a dividend (RR) by a divisor (RD) to calculate an eventual quotient (Q) which has a plurality of digits, N in number, and is divisible into first through N-th partial quotients (Q 1 , Q 2 ...Q N ) for the respective digits, said electronic circuit including reciprocal calculating means (34) responsive to said divisor (RD) for calculating an approximate reciprocal (RC) of said divisor (RD), comprises: first calculating means (36) responsive to said divisor (RD) and said approximate reciprocal (RC) for calculating a correction factor (C 1 ) which is equal to a product of said divisor (RD) and said approximate reciprocal (RC); second calculating means (37) responsive to said dividend (RR) and said approximate reciprocal (RC) for calculating a first provisional quotient which is equal to a product of said dividend (RR) and said approximate reciprocal (RC); processing means responsive to said correction factor (C1) and said first provisional quotient (R 1 ) for processing said first provisional quotient (R 1 ) with reference to said correction factor (C 1 ) to produce a succession of said first through said N-th partial quotients (Q 1 ' Q 2 ...Q N ); and collecting means (105) for collecting said succession of first through N-th partial quotients (Q 1 , Q 2 ...Q N ) into said eventual quotient (Q).

Claim 3

An electronic circuit as claimed in claim 1, wherein said processing means comprises: means (61) responsive to said first provisional quotient (R 1 ) for producing a first partial provisional quotient (P 1 ) related to said first partial quotient (Q 1 ); provisional quotient calculating means (64 1 , 64 2 , ... 64 N )responsive to said first provisional quotient (R 1 ), said correction factor (C 1 ), and said first partial provisional quotient (P 1 )for sucessively calculating second through (N+1)-th provisional quotients (R 2 , R 3 ,... R N +1); means (91 1 , 91 2 ,...,91 N-1 ) responsive to a succession of said second through said N-th provisional quotients (R 2 , R 3 ,...,R N ) for successively deciding second through N-th partial provisional quotients (P 2 ' P 3 ...P N ) related to said second through said N-th provisional quotients (R 2 , R 3 ,...,R N ), respectively; and means (66 1 , 66 2 ,...,66 N ) responsive to said first through said N-th partial provisional quotients (P 1 , P 2 ,,..,P N ) and said second through (N+1)-th provisional quotient (R 2 , R 3 '...,R N+1 ) and coupled to said provisional quotient calculating means (64 2 , 64 3 ,...,64 N ) for successively correcting said first through said N-th partial provisional quotients (P 1 , P 2 ,...,P N ) into said first through said N-th partial quotients (Q 1' Q 2 ,...,Q N ) in consideration of said second through said (N+1)-th provisional quotients (R 2 , R 3 ,...,R N+1 ), respectively.

Claim 4

An electronic circuit as claimed in claim 2, wherein said provisional quotient calculating means comprises: first through N-th calculating means (64 1 , 64 2 ,..., 64 N ) connected in cascade to one another for successively producing said second through said (N+1)-th provisional quotients (R 2 , R 3 ,...,R N+1 ) with reference to said correction factor (C 1 ); said first calculation means (64 1 ) being supplied with said first provisional quotient (R 1 ).

Claim 5

An electronic circuit as claimed in any of claims 1 to 3, wherein said collecting means comprises: mcans (105) for synchronously producing said succession of first through N-th partial quotients (Q 1 , Q 2 ,...,Q N ) as said eventual quotient (Q).