Modular data processing system

Claim 1

A modular data processing system having a plurality of discrete functional hardware circuit modules, each circuit module being connected to a common system bus and at least part of the modules having control circuitry for intermodule communication in which they perform particular tasks using distributive processing technique, each of these modules having a central processing unit (CPU), characterized by said control circuitry comprising: interrupt register means (302) and response port means (300) in each of'the modules; means (IOWC) for writing a given code into the response port of the target module; means (IORC) in the calling module for reading the code in the response port of the target module; and means (IOWC) in the calling module for loading the interrupt register in the target module with a multi-bit vector only if said calling module has read said code from the response port of the target module; and means (RDIR) for causing the target module to read the vector stored in said interrupt register whereby said target module is caused to perform a task associated with said multi-bit vector.

Claim 5

The system of one of the claims 1 to 3 further including a plurality of modules having vectored interrupt circuitry (210) comprising: latch means (240) coupled to data lines on the system bus, said latch containing a predetermined multibit code defining a vector associated with a particular memory location accessible by a calling module; an interrupt priority line (212) coupled in a daisy chain fashion to other modules in the system; first storage device means (214) for asynchronously storing an internally generated interrupt request from the module; second storage device means (224) having an input coupled to the output of said first storage device, an output, and a clock input operative to transfer information on the second flip flop input to its output upon receipt of a signal at the clock input thereof; interrupt line gating means (226) having inputs coupled for receipt of said interrupt priority line and the output from said second storage device, said interrupt gating means having an output adapted to be coupled to the input of the interrupt line of the next module; and means for coupling a clock signal (Ml) from the calling module to the clock input of said second storage device whereby to control the state of the interrupt priority lines of the other modules, said vectored interrupt circuitry further consists of enabling gating means (236) having a plurality of inputs, and an output coupled to said latch, operative to control the placement of said vector contained in the latch over the system bus to the calling module depending upon the state of the signals at the enabling gating means input, said enabling gating means input being coupled to the output of said second storage device, the interrupt priority line, and an acknowledge signal (INTA) from said calling module.