Electronically selectable redundant array (ESRA)

Claim 2

Test circuit means contained on an integrated circuit chip containing interconnected logic circuit means and memory array circuit means, said test circuit means comprising: level sensitive scan design circuit means (the SRL's 1-4) connected to said logic circuit means and said array circuit means, said level sensitive scan design circuit means being utilized at least in part for determining the merit or lack of merit of said logic circuit means and/or said memory array circuit means contained on said integrated circuit chip; and characterized by: additional controllable circuit means (the RWP's) included within said level sensitive scan design circuit means, said additional controllable circuit means modifying the operation of said level sensitive scan design circuit means at least partially in response to a control signal; control circuit means (G1-4) interconnecting and cooperating with said memory array circuit means, said additional circuit means and said level sensitive scan design circuit means, said control circuit means providing said control signal and in cooperation with said additional controllable circuit means obviating at least one lack of merit condition manifested by said array circuit means.

Claim 3

An integrated circuit containing an n x m read/write memory array, wherein n and m are respectively positive integers and said memory array having the capacity to store m words, each of said words having n bits, said array including: m storage means, each of said m storage means having an input and an output, each of said m storage means having the capacity to store a word having n binary bits; m memory array inputs (R), each of said m memory array inputs corresponding to one of said m storage means and connected to the input thereof; at least one additional (or redundant) storage means, each of said additional storage means having an input and an output, each said additional storage means having the capacity to store a word having n binary bits; m memory array outputs (D), each of said m memory array outputs corresponding to one of said m storage means; level sensitive scan design circuit means (SRLI-4) connected to said outputs of said m storage means and said m memory array outputs (D); characterized by said output of said at least one additional storage means being connected to each of said level sensitive scan design circuit means, and said level sensitive scan design circuit means including means for storing a predetermined binary bit pattern indicative of which of said m storage means, if any, is defective; logic circuit means having a first group of inputs, a second group of inputs and an output, said first group of inputs being selectively connected to said m inputs (R) of said m storage means, said second group of inputs being selectively connected to outputs (Gl-4) of said level sensitive scan design circuit means, said output of said logic circuit means being connected to said input of one of said additional storage means, said logic circuit means being controlled by said predetermined binary bit pattern stored in said storage means of said level sensitive scan design circuit means, whereby said predetermined binary bit pattern is effective in causing any predetermined defective one of said m storage means to be replaced by one of said additional storage means without any effect or modification on the function or designation of the m memory array inputs and m memory outputs.

Claim 4

An integrated circuit containing an n x m read/write memory array, wherein n and m are respectively positive integers and said memory array having the capacity to store m words, each of said words having n bits, said array including: m storage means, each of said m storage means having an input and an output, each of said m storage means having the capacity to store a word having n binary bits; m memory array inputs (R), each of said m memory array inputs corresponding to one of said m storage means and connected to the input thereof; at least one additional (or redundant) storage means, each of said additional storage means having an input and an output, each said additional storage means having the capacity to store a word having n binary bits; m memory array outputs (D), each of said m memory array outputs corresponding to one of said m storage means; level sensitive scan design circuit means (SRLI-4) connected to said outputs of said m storage means and said m memory array outputs (D); characterized by said output of said at least one additional storage means being connected to each of said level sensitive scan design circuit means, and said level sensitive scan design circuit means including means for storing a predetermined binary bit pattern indicative of which of said m storage means, if any, is defective; logic circuit means having a first group of inputs, a second group of inputs and an output, said first group of inputs being selectively connected to said m inputs (R) of said m storage means, said second group of inputs being selectively connected to outputs (Gl-4) of said level sensitive scan design circuit means, said output of said logic circuit means being connected to said input of one of said additional storage means, said logic circuit means being controlled by said predetermined binary bit pattern stored in said storage means of said level sensitive scan design circuit means, whereby said predetermined binary bit pattern is effective in causing any predetermined defective one of said m storage means to be replaced by one of said additional storage means without any effect or modification on the function or designation of the m memory array inputs and m memory outputs.

Claim 5

An integrated circuit containing an n x m read/write memory array, as recited in claim 2, wherein each of said m storage means and said at least one additional storage means contains n memory cells and each of said memory cells is capable of storing one binary bit of data.

Claim 6

An integrated circuit containing an n x m read/write memory array, as recited in claim 3, wherein said level sensitive scan design circuit means includes m shift register latches (SRL's), each of said shift register latches being capable of storing at least one binary bit of data, said shift register latches being utilized to store said predetermined binary bit pattern.

Claim 7

An integrated circuit containing an n x m read/write memory array, as recited in claim 4, wherein said m shift register latches of said level sensitive scan design circuitry are interconnected into an m stage shift register having a scan input, a scan output and control circuitry for shifting said predetermined bit pattern into and out of said shift register.

Claim 8

An integrated circuit containing an n x m read/write memory array, as recited in claim 5, wherein each of said m shift register latch circuits includes interconnected first (Ll) and second (L2) latch circuits and said predetermined binary bit pattern is stored in said m second (L2) latches of said m stage shift register.

Claim 9

An integrated circuit containing an n x m read/write memory array, as recited in claim 6, wherein each of said m first (L1) latch circuits includes a word data port and a redundant word data port (RWP), and each of said m second (L2) latch circuits includes at least one data port.

Claim 10

An integrated circuit containing an n x m read/write memory array, as recited in claim 7, wherein each of said m. first (Ll) latch circuits has an output connected to a discrete one of said m memory array outputs (D), each of said m second (L2) latch circuits has a first output (+L2) connected to said word data port of the first (Ll) latch circuit contained within said same shift register latch as said second (L2) latch circuit, each of said m second (L2) latch circuits has a second output (-L2) connected to said redundant word data port of the first (Ll) latch circuit contained within said same shift register latch as said second latch (L2) circuit.

Claim 11

An integrated circuit containing an n x m read/write memory array, as recited in claim 8, wherein each of said outputs of said m storage means is connected to the word data port of a predetermined one of said first (LI) latch circuits of said m stage shift register, and wherein said output of one of said additional (or redundant) storage means is connected in common to the redundant word data port of each of said first (Ll) latch circuits of said m stage shift register.

Claim 12

An integrated circuit containing an n x m read/write memory array, as recited in claim 9, wherein said first group of inputs of said logic circuit means consists of m inputs, each of said m inputs of said first group of inputs of said logic circuit means being connected to a discrete one of said m inputs (R) of said m storage means, and wherein said second group of inputs of said logic circuit means consists of m inputs, each of said m inputs of second group of inputs of said logic circuit means being connected to a predetermined one of said second (L2) latch circuits of said m stage shift register.

Claim 13

An integrated circuit containing an n x m read/write memory array, as recited in claim 10, wherein said control circuitry for shifting said predetermined bit pattern into and out of said m stage shift register includes scan circuit means adapted to receive an A-clock signal and a B-clock signal.

Claim 14

An integrated circuit containing an n x m read/write memory array, as recited in claim 11, wherein said word data port and said redundant - word data port (RWP) of each of said first (L1) latch circuits of said m shift register latch circuits is adapted to receive a system (or C) clock.