EP0164781A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
A self-aligned split gate EPROM and a method of manufacturing the same
Assignee: WAFER SCALE INTEGRATION Inc
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Filing: 1985-05-10
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Granted: —
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Expires: 2005-05-10
Abstract
Abstract A self-aligned split gate single transistor memory cell structure is formed by a process which self aligns the drain region to one edge of a floating gate. The portion of the channel underneath the floating gate is accurately defined by using one edge of the floating gate to align the drain region. The control gate formed over the floating gate controls the portion of the channel region between the floating gate and the source to provide split gate operation. The source region is formed sufficiently far from the floating gate that the channel length between the source region and the closest edge of the floating gate is controlled by the control gate but does not have to be accurately defined.
Inventors
- 👤 Boaz Eitan
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 09:01
CPC Classifications
H; H10; H10B; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D64/00; H10D64/01; H10D64/031; H10D64/035
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
142 words
A self-aligned split gate single transistor memory cell for a programmable read only memory comprising a semiconductor substrate containing a source region and a drain region separated by a channel region; a floating gate formed over but separated by insulation from a first portion of the channel region, said floating gate including a first edge and a second edge, said second edge of said floating gate being over said channel region and separated from the closest edge of said source region by a second portion of said channel region; and a control gate formed over but insulated from said floating gate and formed over but insulated from said second portion of said channel region, said memory cell being characterized in that - said first edge of the floating gate is aligned with and used to define one edge of said drain region.
Claim 2
Dependent Claim
142 words
A self-aligned split gate single transistor memory cell for a programmable read only memory comprising a semiconductor substrate containing a source region and a drain region separated by a channel region; a floating gate formed over but separated by insulation from a first portion of the channel region, said floating gate including a first edge and a second edge, said second edge of said floating gate being over said channel region and separated from the closest edge of said source region by a second portion of said channel region; and a control gate formed over but insulated from said floating gate and formed over but insulated from said second portion of said channel region, said memory cell being characterized in that - said first edge of the floating gate is aligned with and used to define one edge of said drain region.
Claim 3
Dependent Claim
55 words
Structure as in Claim 1 further characterized in that the portion of said control gate overlying said second portion of said channel region is separated from the second portion of said channel region by insulation of approximately the same thickness as the insulation separating said floating gate from said first portion of said channel region.
Claim 4
Dependent Claim
68 words
Structure as in Claim 1 further characterized in that the minimum length of said second portion of said channel region from said source region to said floating gate is a function of the alignment tolerances on the manufacturing process used to make said memory cell and wherein the length of said second portion of said channel can vary by substantial amounts without affecting the performance of said cell.
Claim 5
Dependent Claim
36 words
Structure as in Claim 3 further characterized in that the length of said second portion of said channel region can vary by in excess of 1 micron without substantially affecting the performance of the memory cell.
Claim 6
Dependent Claim
50 words
Structure as in Claim 1 further characterized in that said floating gate has a portion which extends over a portion of said drain due to the lateral diffusion of said drain region under said floating date during the processing of said memory cell after the formation of said drain region.
Claim 7
Dependent Claim
35 words
Structure as in Claim 1 further characterized in that said single transistor memory cell is part of an array of such cells each cell having approximately the same effective channel length underneath its floating gate.
Claim 8
Dependent Claim
41 words
Structure as in Claim 1 further characterized in that said floating gate is formed prior to the drain region and the drain region is then formed using one edge of the floating gate to define one edge of the drain region.
Claim 9
Independent Claim
163 words
The method of manufacturing a single transistor self-aligned-memory cell characterized by the steps comprising forming a first portion of polycrystalline silicon on, but separated from a semiconductor substrate by first insulation, said first portion of polycrystalline silicon comprising a floating gate having a first edge and a second edge opposite said first edge; forming a photoresist pattern over the surface of said polycrystalline silicon and said substrate, an opening being formed in said photoresist pattern to expose both the first edge of said floating gate and a portion of the semiconductor substrate beyond said first edge and also to expose a portion of the semiconductor substrate beyond the second edge of said floating gate; and implanting selected impurities into that portion of the semiconductor substrate exposed by the removal of portions of said photoresist thereby to form a source region beyond the second edge of said floating gate and a drain region beyond but self-aligned to the first edge of said floating gate.
Claim 10
Independent Claim
163 words
The method of manufacturing a single transistor self-aligned-memory cell characterized by the steps comprising forming a first portion of polycrystalline silicon on, but separated from a semiconductor substrate by first insulation, said first portion of polycrystalline silicon comprising a floating gate having a first edge and a second edge opposite said first edge; forming a photoresist pattern over the surface of said polycrystalline silicon and said substrate, an opening being formed in said photoresist pattern to expose both the first edge of said floating gate and a portion of the semiconductor substrate beyond said first edge and also to expose a portion of the semiconductor substrate beyond the second edge of said floating gate; and implanting selected impurities into that portion of the semiconductor substrate exposed by the removal of portions of said photoresist thereby to form a source region beyond the second edge of said floating gate and a drain region beyond but self-aligned to the first edge of said floating gate.
Claim 11
Dependent Claim
25 words
The method of Claim 8 further characterized in that said drain region has a selected edge self-aligned to the first edge of said floating gate.
Claim 12
Independent Claim
85 words
The method of manufacturing a programmable read only memory characterized by comprising forming a floating gate over a portion of a channel region between a source and a drain in a semiconductor substrate wherein the length of the effective channel beneath the floating gate between the source and the drain is controlled to have a value sufficiently small to minimize the drain voltage at which programming begins but not so small as to create a danger of punch through between the source and the drain.
Claim 13
Independent Claim
85 words
The method of manufacturing a programmable read only memory characterized by comprising forming a floating gate over a portion of a channel region between a source and a drain in a semiconductor substrate wherein the length of the effective channel beneath the floating gate between the source and the drain is controlled to have a value sufficiently small to minimize the drain voltage at which programming begins but not so small as to create a danger of punch through between the source and the drain.
References Cited (Backward Citations)
No citation records indexed.
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