EP0165600A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Input/output bus for computer
Assignee: Convex Computer Corp
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Filing: 1985-06-19
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Granted: —
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Expires: 2005-06-19
Abstract
Abstract A communication bus (14) provides bidirectional data communication between a computer (12) and various peripheral units including input/output processors (18, 20) and a service processor (22). The computer includes a memory control unit (24) which is connected to a memory array (26). A central processor unit (30) is connected for data exchange with the memory-control unit (24). Data blocks are transferred through the bus (14) and either originate or terminate at the memory array (26). A peripheral unit, such as the processor (18) transfers a data block by first transferring a header parcel (146) which defines an address, block length and type of function. This is transmitted to the memory control unit (24) which carries out the desired data transfer by sending or receiving sequential data parcels. An interrupt bus (16) connects each of the units of the computer system (10) including the processors (18, 20, 22) and the central processing unit (30). Any one of the units connected to the interrupt bus (16) can interrupt any of the other units. The interrupt process comprises sending an interrupt vector through interrupt lines (66). At the receiving unit the interrupt is identified and the appropriate function carried out. The combination of the communication bus and the interrupt bus (16) comprises an input/output bus for the computer system (10) to provide a high data bandwidth together with flexible operation.
Inventors
- 👤 Alan D. Gant
- 👤 David A. Nobles
- 👤 Thomas M. Jones
- 👤 Arthur T. Kimmel
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-25 06:27
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/24; G06F13/26; G06F13/28; G06F13/36; G06F13/362; G06F13/364; G06F13/38; G06F13/42; G06F13/4204; G06F13/4208; G06F13/4217; G06F15/00; G06F15/16; G06F15/163; G06F15/17
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
140 words
A method for data communication via a bus connecting a computer to one or more peripheral units, comprising the steps of: requesting to a bus arbiter use of said bus by one of said peripheral units, granting use of said bus by said bus arbiter to said one peripheral unit in response to said step of requesting, generating a header parcel comprising an address for a data block to be transferred between said computer and said one peripheral unit, a count indicating the size of said data block and a command code indicating the type of transfer for said data block, transmitting said header parcel from said one peripheral unit via said bus to said computer after said step of granting, and sequentially transmiting parceld of caid data block via said bus between said computer and said one peripheral unit.
Claim 2
Independent Claim
140 words
A method for data communication via a bus connecting a computer to one or more peripheral units, comprising the steps of: requesting to a bus arbiter use of said bus by one of said peripheral units, granting use of said bus by said bus arbiter to said one peripheral unit in response to said step of requesting, generating a header parcel comprising an address for a data block to be transferred between said computer and said one peripheral unit, a count indicating the size of said data block and a command code indicating the type of transfer for said data block, transmitting said header parcel from said one peripheral unit via said bus to said computer after said step of granting, and sequentially transmiting parceld of caid data block via said bus between said computer and said one peripheral unit.
Claim 3
Dependent Claim
61 words
The method recited in Claim 1 wherein said step of requesting comprises applying a predetermined logic state by said one peripheral unit to a request line which connects said one peripheral unit to said bus arbiter and said step of granting comprises applying a predetermined logic state to a grant line which connects said bus arbiter to said one peripheral unit.
Claim 4
Dependent Claim
32 words
The method as recited in Claim 1 wherein said step of sequentially transmitting comprises transmitting said parcels of said data block from said one peripheral unit to a memory within said computer.
Claim 5
Dependent Claim
53 words
The method as recited in Claim 3 including the step of generating a sequence of addresses derived from said address received in said header parcel, each sequential address corresponding to one of said parcels of said data block, each parcel of said data block stored in said memory at the corresponding sequential address.
Claim 6
Dependent Claim
33 words
The method as recited in Claim 1 wherein said step of sequentially transmitting comprises transmitting said parcels of said data block from a memory in said computer to said one peripheral unit. -
Claim 7
Dependent Claim
38 words
The method recited in Claim 5 including the step of generating a sequence of addresses derived from said address received in said header.parcel, each of said sequential address corresponding to a unit of data read from said memory.
Claim 8
Dependent Claim
48 words
The method as recited in Claim 1 including the step of arbitrating by said bus arbiter the multiple requesting ot use of said bus, said arbitrating comprising awarding said granting of use to said peripheral units on a rotary basis and to said computer on a priority basis.
Claim 9
Dependent Claim
282 words
8, A method for data communication via a bus connecting a computer to one or more peripheral units, comprising the steps of: requesting to a bus arbiter use of said bus by one of said peripheral units, granting use of said bus by said bus arbiter to said one peripheral unit in response to said step of requesting, generating a header parcel comprising an address for a data block to be transfined between said computer and said one peripheral unit, a count indicating the size of said data block and a command code indicating the type of transfer for said data block, transmitting said header parcel from said one peripheral unit via said bus to said computer after said step of granting, sequentially transmitting parcels of said data block via said bus between said computer and said one peripheral unit, maintaining a count of the number of units of said data block remaining to be transmitted between said computer and said one peripheral unit, terminating transfer of said data block between said computer and said one peripheral unit prior to the transfer of the entirety of said data block, generating a new header parcel comprising a new address determined from said address for said data block and said remaining count of the number of units of said data block at the time of the terminating of said transfer of said data block, said remaining count and said command code, and repeating said steps of requesting and granting, . transmitting said new header parcel from said one peripheral unit to said computer, and sequentially transmitting the remaining parcels of said data block via said bus between said computer and said one peripheral unit.
Claim 10
Dependent Claim
282 words
8, A method for data communication via a bus connecting a computer to one or more peripheral units, comprising the steps of: requesting to a bus arbiter use of said bus by one of said peripheral units, granting use of said bus by said bus arbiter to said one peripheral unit in response to said step of requesting, generating a header parcel comprising an address for a data block to be transfined between said computer and said one peripheral unit, a count indicating the size of said data block and a command code indicating the type of transfer for said data block, transmitting said header parcel from said one peripheral unit via said bus to said computer after said step of granting, sequentially transmitting parcels of said data block via said bus between said computer and said one peripheral unit, maintaining a count of the number of units of said data block remaining to be transmitted between said computer and said one peripheral unit, terminating transfer of said data block between said computer and said one peripheral unit prior to the transfer of the entirety of said data block, generating a new header parcel comprising a new address determined from said address for said data block and said remaining count of the number of units of said data block at the time of the terminating of said transfer of said data block, said remaining count and said command code, and repeating said steps of requesting and granting, . transmitting said new header parcel from said one peripheral unit to said computer, and sequentially transmitting the remaining parcels of said data block via said bus between said computer and said one peripheral unit.
Claim 11
Dependent Claim
61 words
The method recited in Claim 8 wherein said step of requesting comprises applying a predetermined logic state by said one peripheral unit to a request line which connects said one peripheral unit to said bus arbiter and said step of granting comprises applying a predetermined logic state to a grant line which connects said bus arbiter to said one peripheral unit.
Claim 12
Dependent Claim
32 words
The method as recited in Claim 8 wherein said step of sequentially transmitting comprises transmitting said parcels of said data block from said one peripheral unit to a memory within said computer.
Claim 13
Dependent Claim
53 words
The method as recited in Claim 10 including the step of generating a sequence of addresses derived from said address received in said header parcel, each sequential address corresponding to one of said parcels of said data block, each parcel of said data block stored in said memory at the corresponding sequential address.
Claim 14
Dependent Claim
32 words
The method as recited in Claim 8 wherein said step of sequentially transmitting comprises transmitting said parcels of said data block from a memory in said computer to said one peripheral unit.
Claim 15
Dependent Claim
40 words
The method as recited in Claim 8 including the step of generating a sequence of addresses derived from said address received in said header parcel, each of said sequential addresses corresponding to a unit of data read from said memory.
Claim 16
Independent Claim
115 words
A method for providing interrupts in a computer system having a central processor unit and one or more peripheral units, comprising the steps of; requesting to a bus arbiter use of an interrupt bus by a first of said central processor unit or said peripheral units, said interrupt bus connected to each of said units, granting use of said interrupt bus by said bus arbiter to said first unit, transmitting from said first unit via said interrupt bus to a second of said central processor unit or peripheral units a vector interrupt signal which corresponds to said second unit, and acknowledging receipt of said vector interrupt signal by said second unit to said first unit.
Claim 17
Independent Claim
115 words
A method for providing interrupts in a computer system having a central processor unit and one or more peripheral units, comprising the steps of; requesting to a bus arbiter use of an interrupt bus by a first of said central processor unit or said peripheral units, said interrupt bus connected to each of said units, granting use of said interrupt bus by said bus arbiter to said first unit, transmitting from said first unit via said interrupt bus to a second of said central processor unit or peripheral units a vector interrupt signal which corresponds to said second unit, and acknowledging receipt of said vector interrupt signal by said second unit to said first unit.
Claim 18
Dependent Claim
51 words
- 15. The method recited in Claim 14 including the step of arbitrating by said bus arbiter the multiple requesting of use of said interrupt bus, said arbitrating comprising awarding said granting of use to said peripheral units on a rotary basis and to said central processor on a priority basis.
Claim 19
Dependent Claim
185 words
An input/output bus system for providing communication;between a computer and one or more peripheral units, comprising: - a plurality of address/data lines connected in parallel to said computer and said peripheral units for bidirectional transmission of addresses and data through said lines, a bus arbiter, a request and grant line for each of said computer and said peripheral units, said request and grant lines connecting the respective computer and peripheral units to said bus artiber, a plurality of data handshake line connecting said computer to said peripheral units, means within each of said peripheral units for generating a header parcel for transmission through said address/data lines to said computer, said header parcel comprising an address for a data block to be transferred between said computer and one of said peripheral units, a count indicating the size of said data block and a command code for indicating the type of transfer for said data block, storage means within each of said peripheral units and said computer, and means for transferring parcels of said data block via said address/data lines between said computer and said peripheral units.
Claim 20
Dependent Claim
185 words
An input/output bus system for providing communication;between a computer and one or more peripheral units, comprising: - a plurality of address/data lines connected in parallel to said computer and said peripheral units for bidirectional transmission of addresses and data through said lines, a bus arbiter, a request and grant line for each of said computer and said peripheral units, said request and grant lines connecting the respective computer and peripheral units to said bus artiber, a plurality of data handshake line connecting said computer to said peripheral units, means within each of said peripheral units for generating a header parcel for transmission through said address/data lines to said computer, said header parcel comprising an address for a data block to be transferred between said computer and one of said peripheral units, a count indicating the size of said data block and a command code for indicating the type of transfer for said data block, storage means within each of said peripheral units and said computer, and means for transferring parcels of said data block via said address/data lines between said computer and said peripheral units.
Claim 21
Dependent Claim
40 words
The system recited in Claim 16 including means within said computer for generating a sequence of addresses derived from said data block address received in said header parcel, said sequence of addresses corresponding to said parcels of said data block.
Claim 22
Dependent Claim
34 words
The system recited in Claim 16 including within each of said peripheral units a means for maintaining a count of the units of said data block transmitted between said computer and said peripheral unit.
Claim 23
Dependent Claim
97 words
The system recited in Claim 18 wherein said means for generating a header parcel includes means connected to receive said count for producing a new header parcel when the transfer of said data block has been terminated before completion, said new header parcel including a new address derived from the address for said data block and said count, said count for indicating the size of the remainder of the data block and said command code, said new header parcel for transmission from the generating peripheral unit to said computer to complete the transfer of said data block.
Claim 24
Dependent Claim
124 words
An interrupt bus system for providing interrupts between a central processor unit and one or more peripheral units, comprising: an interrupt bus connected in parallel with each said units, a bus arbiter, means for conveying a bus request signal and bus grant signal between each of said units and said bus arbiter, means within each of said units for generating an interrupt vector signal for identifying any of said units to cause an interrupt to occur at the identified unit, said interrupt vector signal transmitted through said interrupt bus, and means within each of said units for recognizing said vector signal transmitted through said interrupt bus and corresponding to the recognizing unit and for generating an interrupt signal upon recognition of said vector signal.
Claim 25
Dependent Claim
124 words
An interrupt bus system for providing interrupts between a central processor unit and one or more peripheral units, comprising: an interrupt bus connected in parallel with each said units, a bus arbiter, means for conveying a bus request signal and bus grant signal between each of said units and said bus arbiter, means within each of said units for generating an interrupt vector signal for identifying any of said units to cause an interrupt to occur at the identified unit, said interrupt vector signal transmitted through said interrupt bus, and means within each of said units for recognizing said vector signal transmitted through said interrupt bus and corresponding to the recognizing unit and for generating an interrupt signal upon recognition of said vector signal.
Claim 26
Dependent Claim
31 words
The interrupt bus system recited in Claim 20 wherein said means for conveying comprises a request line and a grant line converted to said bus arbiter for each of said units.
Claim 27
Dependent Claim
27 words
The interrupt system recited in Claim 20 including means within each of said units for acknowleding receipt of said vector signal when recognized by the receiving unit.
References Cited (Backward Citations)
No citation records indexed.
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