EP0166540A2
Expired / Lapsed
EP
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A semiconductor memory device
Assignee: Fujitsu Ltd
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Filing: 1985-05-30
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Granted: —
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Expires: 2005-05-30
Abstract
Abstract A semiconductor memory device includes at least a pair of bit lines (BL, BL), a word line (WL), a pair of load transistors each connected to the bit lines (Q 5 , Q 6 ), a memory cell (MC) connected to the bit lines and the word line and selected by an address signal, and an equalizing circuit (EQ') connected between each of the bit lines. According to the present invention, the equalizing circuit comprises a P-channel type MIS transistor (Qp) and a N-channel type MIS transistor (Q N ) each connected in parallel. The P-channel type MIS transistor and the N-channel type MIS transistor are temporarily turned ON in response to a change of the address signal. In this way complete equalization of the respective potentials of the two bit lines can be achieved and access time to the memory cell can thereby be shortened as compared with the prior art.
Inventors
- 👤 Keizo Aoyama
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 15:09
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C7/00; G11C7/12; G11C8/00; G11C8/18
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
159 words
A semiconductor memory device comprising selectively addressable memory cells (MC), each of which is connected with a pair of signal lines for receiving respective complementary signals corresponding to information stored in the cell when it is addressed, which two signal lines are interconnected by a MIS transistor, there being switching means (0) connected to the said MIS transistor and operable to render it conductive ("ON") temporarily in response to a change of a memory cell addressing signal so as to bring the respective potentials of the said two signal lines towards equality with one another, characterised in that the said MIS transistor is one of a pair of such transistors(Q N , Qp) which are connected in parallel with one another and are both rendered conductive temporarily in response to the said change of the said addressing signal, one of which transistors is of the P-channel type (Qp) and the other is of the N-channel type (Q N ).
Claim 2
Dependent Claim
159 words
A semiconductor memory device comprising selectively addressable memory cells (MC), each of which is connected with a pair of signal lines for receiving respective complementary signals corresponding to information stored in the cell when it is addressed, which two signal lines are interconnected by a MIS transistor, there being switching means (0) connected to the said MIS transistor and operable to render it conductive ("ON") temporarily in response to a change of a memory cell addressing signal so as to bring the respective potentials of the said two signal lines towards equality with one another, characterised in that the said MIS transistor is one of a pair of such transistors(Q N , Qp) which are connected in parallel with one another and are both rendered conductive temporarily in response to the said change of the said addressing signal, one of which transistors is of the P-channel type (Qp) and the other is of the N-channel type (Q N ).
Claim 3
Dependent Claim
103 words
A semiconductor memory device comprising a memory cell (MC) selected by an address signal (ADD), at least a pair of signal lines for receiving a complementary signal corresponding to information stored in said memory cell, and an equalizing circuit (EQ') connected between each of said signal lines for equalizing the potential of said signal lines, wherein said equalizing circuit comprises a P-channel type MIS transistor (Qp) and an N-channel type MIS transistor (Q N ) each connected in parallel, said P-channel type MIS transistor and said N-channel type MIS transistor being temporarily turned ON in response to a change of said address signal.
Claim 4
Dependent Claim
103 words
A semiconductor memory device comprising a memory cell (MC) selected by an address signal (ADD), at least a pair of signal lines for receiving a complementary signal corresponding to information stored in said memory cell, and an equalizing circuit (EQ') connected between each of said signal lines for equalizing the potential of said signal lines, wherein said equalizing circuit comprises a P-channel type MIS transistor (Qp) and an N-channel type MIS transistor (Q N ) each connected in parallel, said P-channel type MIS transistor and said N-channel type MIS transistor being temporarily turned ON in response to a change of said address signal.
Claim 5
Dependent Claim
48 words
A semiconductor memory device as claimed in claim 1 or 2, wherein, in the turning ON timing of said P-channel and N-channel type MIS transistors (Q P , Q N ), said P-channel type MIS transistor is turned ON before said N-channel type MIS transistor is turned ON.
Claim 6
Dependent Claim
49 words
A semiconductor memory device as claimed in claim 1, 2 or 3, wherein, in the turning OFF timing of said P-channel and N-channel type MIS transistors (Q P , Q N ) said P-channel type MIS transistor is turned OFF before said N-channel type MIS transistor is turned OFF.
Claim 7
Dependent Claim
31 words
A semiconductor memory device as claimed in any preceding claim, wherein said pair of signal lines is a pair of bit lines (BL, BL ) connected to said memory cell (MC).
Claim 8
Dependent Claim
32 words
A semiconductor memory device as claimed in claim 1, 2, 3 or 4, wherein said pair of signal lines is a pair of data bus lines (D 1 , D 2 ).
References Cited (Backward Citations)
No citation records indexed.
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