EP0166966A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Video display controller
Assignee: Yamaha Corp
•
Filing: 1985-05-29
•
Granted: —
•
Expires: 2005-05-29
Abstract
Abstract A video display processor (VDP) produces a video signal by which a black and white image of an increased gradation can be displayed on a video display unit. The VDP reads from a video RAM (VRAM) color codes each representative of a color of each display element or amplitude data representative of amplitudes of a video signal to be reproduced. In the case of displaying an image based on the color codes, the color codes, are converted by a color palette circuit into color data each composed of three primary color data, and then supplied to a digital color encoder. The digital color encoder multiplies each of the three color data by predetermined coefficients at proper phase timings to output data representative of three chrominance signals. These data outputted from the color encoder are added together by an adder circuit and then converted into an analog signal to be supplied to the video display unit as the video signal. On the other hand, in the case of displaying an image based on the amplitude data, the color palette circuit converts the amplitude data into gradation data. The digital color encoder multiplies the gradation data by other proper coefficients so that data proportional in value to the gradation data are obtained at the output of the adder circuit. The thus obtained data are also converted into an analog signal to thereby reproduce the video signal. The VDP also comprises a color burst generator which generates under the control of a central processing unit a color burst signal to be added to the output of the digital color encoder.
Inventors
- 👤 Nishi C/O Ascii Corporation Kazuhiko
- 👤 Ishii C/O Ascii Corporation Takatoshi
- 👤 Yamashita C/O Ascii Corporation Ryozo
- 👤 Okumura Takatoshi
- 👤 Yamaoka Shigemitsu
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 10:09
CPC Classifications
G; G09; G09G; G09G1/00; G09G1/28; G09G1/285; G09G5/00; G09G5/02; G09G5/06
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
216 words
A video display controller for use with a video display unit, a central processing unit and memory means for storing a plurality of image data, to display on a screen of the video display unit an image composed of a plurality of display elements in accordance with the plurality of image data, said video display controller characterized by the provision of: (a) clock signal generating means for generating a clock signal which is synchronized with display timing of the display elements on the screen; (b) reading means responsive to said clock signal for reading the plurality of image data from the memory means; (c) phase angle generating means for generating a plurality of phase angle signals synchronized with said clock signal; and (d) encoder means for multiplying said read image data by a plurality of first predetermined coefficients provided therein in response to said plurality of phase angle signals, respectively, to output data representative of a chrominance of a color which is designated by said read image data, said encoder means multiplying said read image data by a second predetermined coefficient provided therein to output data proportional in value to said second coefficient when said phase angle signal is not supplied thereto; (e) said output of said encoder means being supplied to said video display unit.
Claim 2
Dependent Claim
216 words
A video display controller for use with a video display unit, a central processing unit and memory means for storing a plurality of image data, to display on a screen of the video display unit an image composed of a plurality of display elements in accordance with the plurality of image data, said video display controller characterized by the provision of: (a) clock signal generating means for generating a clock signal which is synchronized with display timing of the display elements on the screen; (b) reading means responsive to said clock signal for reading the plurality of image data from the memory means; (c) phase angle generating means for generating a plurality of phase angle signals synchronized with said clock signal; and (d) encoder means for multiplying said read image data by a plurality of first predetermined coefficients provided therein in response to said plurality of phase angle signals, respectively, to output data representative of a chrominance of a color which is designated by said read image data, said encoder means multiplying said read image data by a second predetermined coefficient provided therein to output data proportional in value to said second coefficient when said phase angle signal is not supplied thereto; (e) said output of said encoder means being supplied to said video display unit.
Claim 3
Dependent Claim
154 words
A video display controller according to claim 1, wherein the read image data comprises a color code representative of a color of the corresponding display element and wherein said video display controller further comprises code converting means for converting said color code into three data representative respectively of three primary colors of said color and data combining means, said encoder means comprising first to third encoders for being supplied with said three data, respectively, each of said first to third encoders being provided with a plurality of first predetermined coefficients and multiplying a corresponding one of said three data by said plurality of first predetermined coefficients in response to said plurality of phase clock signals, respectively, to output data representative of a chrominance of a corresponding one of said three primary colors, said data combining means combining said data outputted from said first to third encoders together to form a digital color video signal.
Claim 4
Dependent Claim
163 words
A video display controller according to claim 2, wherein the read image data further comprises data representative of an amplitude of a video signal corresponding to the image, said code converter means further converting said amplitude data into data representative of gradation of image of the corresponding display element, the number of bits of said gradation data being less than the total number of bits of said three primary color data, said gradation data being supplied to said first to third encoders in parallel in unit of bits equal in number to those of said each primary color data from the MSB thereof, each of said first to third encoders being provided with a second coefficient and multiplying a specific portion of said unit of bits by said second coefficient when said plurality of phase angle signals are not supplied thereto, each of said second coefficients is of such a value that said gradation data appears at the output of said combining means.
Claim 5
Dependent Claim
29 words
A video display controller according to claim 3, wherein each of said three primary color data is composed of three bits, said gradation data being composed of five bits.
Claim 6
Dependent Claim
44 words
A video display controller according to claim 1 further comprising: color burst generating means for generating a color burst in synchronization with said plurality of phase angle signals; and addition means for adding said generated color burst to said output of said encoder means.
Claim 7
Dependent Claim
27 words
A video display controller according to claim 5, wherein said color burst generating means further comprises control means for selectively stopping the generation of said color burst.
Claim 8
Dependent Claim
56 words
A video display controller according to claim 6, wherein said color burst generating means comprises: a plurality of register means each for receiving and retaining data supplied from the central processing unit; and output control means for outputting said data in said plurality of register means in response to said plurality of phase angle signals, respectively.
Claim 9
Dependent Claim
37 words
A video display controller according to claim 5, wherein said color burst generating means further comprises phase control means for controlling phase of said color burst with respect to those of said plurality of phase angle signals.
Claim 10
Dependent Claim
77 words
A video display controller according to claim 8, wherein said color burst generating means comprises: a plurality of register means each for receiving and retaining data supplied from the central processing unit; and output control means for outputting said data in said plurality of register means in response to said plurality of phase angle signals, respectively; the central processing unit changes said data in said plurality of register means to control the phase of said color burst.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.