Decoder circuit in an IC memory chip

Abstract

Abstract A decoder circuit fabricated in an IC memory chip and provided onto respective word-line (WL) and respective bit-line of an IC memory matrix fabricated in the IC memory chip, for selecting an EPROM cell which is placed on an intersection point of the word-line (WL) and the bit-line, to program a datum into the EPROM cell by using a high power supply voltage when the decoder circuit operates under a programming mode and to read out a datum stored in the EPROM cell by using a low power supply voltage when the decoder circuit operates under a reading mode, receiving an address signal from the exterior of the decoder circuit. The decoder circuit comprises a NAND gate (Q n1 , Q n2 , Q n3 , O nd ) having its load (Q nd ) and a CMOS invertor (Q p3 , Q n5 ). As making the load (Q nd ) of the NAND gate (Q n1 , Q n2 , Q n3 . Q nd ) function as a constant current load, only a variable power supply voltage (V ppi ) which becomes a high and a low voltage according to the programming and the reading mode respectively can be applied to the decoder circuit without applying other elements like a transfer gate and a compensator as required in the prior art.

Inventors

• 👤 Masanobu Yoshida

Bibliographic Details