EP0179651A2
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Semiconductor memory device
Assignee: Mitsubishi Electric Corp
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Filing: 1985-10-22
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Granted: —
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Expires: 2005-10-22
Abstract
Abstract A Semiconductor memory device in accordance with the present invention operates in response to an address transition detection (ATD) signal for detecting a change in an x address as well as to a write enable signal WE to make the signal level on a selected word line vary according to the read mode and the write mode, whereby dissipation of electric power can be reduced.
Inventors
- 👤 Tomohisa C/O Mitsubishi Denki K.K. Wada
- 👤 Hirofumi C/O Mitsubishi Denki K.K. Shinohara
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 11:25
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/08; G11C8/18
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
129 words
. 1. A semiconductor memory device having a plurality of memory cells connected respectively to a plurality of word lines, operable in the read mode and the write mode according to a write enable signal, said device comprising: decoder means (1 and 2) for decoding an applied address signal to select an associated word line, word line level generating means (40) responsive to said address signal and said write enable signal for generating a signal at a level changing according to the writing and the reading of a selected memory cell, and signal level transmitting means (10 and 20) provided between said decoder means (1 and 2) and said plurality of word lines for transmitting a signal from said word line level generating means to said selected word line.
Claim 2
Dependent Claim
107 words
A semiconductor memory device as set forth in claim 1, wherein said word line level generating means comprises: address change detecting means (30 and 31) for detecting a change in the applied address signal, control signal generating means (32) for generating first and second control signals changing in response to the signal from said address change detecting means and said write enable signal, and a word line level signal generating circuit (4) responsive to said first and second control signals for generating a signal at any level out of relatively high level, relatively low level and a intermediate level between said high level and said low level.
Claim 3
Dependent Claim
59 words
A semiconductor memory device as set forth in claim 1 or claim 2, wherein said signal level transmitting means is an inverter provided between said decoder means and said word line, and the signal from said word line level generating means (40) is applied to one input conduction terminal of a transistor for high level output in said inverter.
Claim 4
Dependent Claim
59 words
A semiconductor memory device as set forth in claims 1, 2 and 3, wherein each of said plurality of word lines is connected with a MOS transistor for pulling down a word line signal level, and a signal as a logical product of said first and second control signals is applied to the gate of said pull-down MOS transistor.
Claim 5
Dependent Claim
54 words
A semiconductor memory device as set forth in claims 1 to 4, wherein the signal from said word line level generating means changes to said relatively high level at the time of reading of a selected memory cell and changes to said intermediate level at the time of writing of said selected memory cell.
Claim 6
Dependent Claim
21 words
A semiconductor memory device as set forth in claims 1 to 5, wherein said semiconductor memory device is a static RAM.
Claim 7
Dependent Claim
114 words
A semiconductor memory device having a plurality of memory cells (3), a plurality of word lines (5) each of which selects a respective plurality of memory cells (3) for reading or writing when the respective word line (5) is selected, and word line selection means (1,2,10,20) which selects a word line according to an address input and connects a word line when selected to an electric potential supply means (40), characterised in that the potential supplied by the electric potential supply means (40) is variable in response to a control input or inputs so that the potential of the selected word line (5) also varies in response to the said control input or inputs.
Claim 8
Dependent Claim
23 words
A semiconductor memory device according to claim 7 in which the control inputs comprise a write enable input and an address signal input.
Claim 9
Dependent Claim
57 words
A semiconductor memory device according to claim 7 or claim 8 in which the variation in the potential of the selected word line (5) has the effect that for a part of the period during which the word line (5) is selected it does not enable the respective plurality of memory cells (3) for reading or writing.
Claim 10
Dependent Claim
87 words
A semiconductor memory device according to any of claims 7 to 9 in which the potential of the selected word line (5) is varied so that for a part of the period during which the word line is selected it has a first potential, at which it enables the respective plurality of memory cells (3), and for another part of the said period it has a second potential which is between the first potential and the potential of the word line (5) when it is not selected.
References Cited (Backward Citations)
No citation records indexed.
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