EP0184547A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Processing method of image data and system therefor
Assignee: Dainippon Screen Manufacturing Co Ltd
•
Filing: 1985-09-23
•
Granted: —
•
Expires: 2005-09-23
Abstract
Abstract The present invention makes it possible to reduce the processing time by dividing an image, which is to be subjected to a processing, into a plurality of sections and subjecting the thus-divided images to an image processing in a limited memory space, especially, by making most effective use of the memory spaces of plural buffer memories to reduce the number of divisions of the original picture when a high-speed affine transformation is performed in the plural buffer memories.
Inventors
- 👤 Tosfumi Inoue
- 👤 Mitsuhiko Yamada
- 👤 Shigeru Miki
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-24 10:32
CPC Classifications
G; G06; G06T; G06T1/00; G06T1/20
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
230 words
A method for processing data on an original picture, which data are stored as image data in a memory having a large capacity and a relatively low access speed, said method including (a) dividing at least one group of the data into a plurality of data portions on the basis of a processable size between two memories capable of performing writing and reading at high speeds, (b) reading out the image data in each data portion from the low-speed memory to perform at least one type of image processing on the read-out image data between the high-speed memories, (c) storing the thus-processed image data again in the low-speed memory, and then (d) performing the above steps (a) through (c) repeatedly on the entirety of the data on the original picture so as to store the processed data on the original picture in the large-capacity and low-speed memory, characterized in that the address control of each of the two memories having the high access speeds and employed in the course of the image processings (a) through (d) is performed in accordance with a multidimensional array, and the processing of the image data between the two memories is performed by changing the address length in each dimension of at least either one of the two memories so as to reduce the number of divisions of the image upon effecting the image processing.
Claim 2
Independent Claim
230 words
A method for processing data on an original picture, which data are stored as image data in a memory having a large capacity and a relatively low access speed, said method including (a) dividing at least one group of the data into a plurality of data portions on the basis of a processable size between two memories capable of performing writing and reading at high speeds, (b) reading out the image data in each data portion from the low-speed memory to perform at least one type of image processing on the read-out image data between the high-speed memories, (c) storing the thus-processed image data again in the low-speed memory, and then (d) performing the above steps (a) through (c) repeatedly on the entirety of the data on the original picture so as to store the processed data on the original picture in the large-capacity and low-speed memory, characterized in that the address control of each of the two memories having the high access speeds and employed in the course of the image processings (a) through (d) is performed in accordance with a multidimensional array, and the processing of the image data between the two memories is performed by changing the address length in each dimension of at least either one of the two memories so as to reduce the number of divisions of the image upon effecting the image processing.
Claim 3
Dependent Claim
46 words
A method according to Claim 1, wherein the address length of each dimension of the memory, the address control of which is performed in accordance with the multidimensional array, is changed depending on the size and shape of an image to be processed at the memory.
Claim 4
Dependent Claim
67 words
A method according to Claim 1 or 2, wherein the address length of each dimension of the memory, the address control of which is performed in accordance with the multidimensional array, is changed independently upon each image processing in such a manner that the number of divisions of the original picture or the number of divisions of the processed image or both of the numbers are minimized.
Claim 5
Independent Claim
73 words
A method according to any one of Claims 1 to 3, wherein address control means for changing the address length of each dimension of the memory, the access control of which is performed in accordance with the multidimensional array, determines each address length in accordance with a parameter which is obtained supposing the product of the address lengths of the individual dimensions be constant and is adapted to change the corresponding address length.
Claim 6
Independent Claim
33 words
A method according to any one of Claims 1 to 4, wherein the address control means is composed of a central processing unit (CPU) which centrally controls the processing of the image data.
Claim 7
Independent Claim
56 words
A method according to any one of Claims 1 to 5, wherein the address designation of the memory, the address control of which is performed in accordance with the multidimensional array, is effected directly by address signals obtained by converting multidimensionally-arrayed indirect address signals, which are adapted to perform the address control, into numerical address signals.
Claim 8
Independent Claim
251 words
A method for processing data on an original picture, which data are stored as image data in a memory having a large capacity and a relatively low access speed, said method including (a) dividing at least one group of the data into a plurality of data portions on the basis of a processable size between two memories capable of performing writing and reading at high speeds, (b) reading out the image data in each data portion from the low-speed memory to perform at least one type of image processing on the read-out image data between the high-speed memories, (c) storing the thus-processed image data again in the low-speed memory, and then (d) performing the above steps (a) through (c) repeatedly on the entirety of the data on the original picture so as to store the processed data on the original picture in the large-capacity and low-speed memory, characterized in that the address control of each of the two memories having the high access speeds and employed in the course of the image processings (a) through (d) is performed in accordance with a multidimensional array and the addresses of at least either one of the two memories are identified by an affine transformation or inverse affine transformation of the addresses of the other memory, whereby the processing of the image data between the two memories is performed in such a way that the image data, which are transferred between both memories, are subjected to the affine transformation or the inverse affine transformation.
Claim 9
Independent Claim
251 words
A method for processing data on an original picture, which data are stored as image data in a memory having a large capacity and a relatively low access speed, said method including (a) dividing at least one group of the data into a plurality of data portions on the basis of a processable size between two memories capable of performing writing and reading at high speeds, (b) reading out the image data in each data portion from the low-speed memory to perform at least one type of image processing on the read-out image data between the high-speed memories, (c) storing the thus-processed image data again in the low-speed memory, and then (d) performing the above steps (a) through (c) repeatedly on the entirety of the data on the original picture so as to store the processed data on the original picture in the large-capacity and low-speed memory, characterized in that the address control of each of the two memories having the high access speeds and employed in the course of the image processings (a) through (d) is performed in accordance with a multidimensional array and the addresses of at least either one of the two memories are identified by an affine transformation or inverse affine transformation of the addresses of the other memory, whereby the processing of the image data between the two memories is performed in such a way that the image data, which are transferred between both memories, are subjected to the affine transformation or the inverse affine transformation.
Claim 10
Dependent Claim
37 words
A method according to Claim 7, wherein the address signals which are subjected to the affine transformation or the inverse affine transformation are the multidimensionally-arrayed address signals adapted to perform the address control of the two memories.
Claim 11
Dependent Claim
79 words
A method according to Claim 7 or 8, wherein addresses of the memory, which receives and stores image data, are successively identified in advance and the addresses are then subjected to the inverse affine transformation so as to designate addresses of the memory to which the image data are sent, whereby image data to be subjected to the affine transformation for storage in the latter memory are retrieved on the memory from which the image data are sent out.
Claim 12
Dependent Claim
65 words
A method according to Claim 7 or 8, wherein when the memory for the reception and storage of image data contains insufficient image data for the affine transformation and subsequent storage, image data to be stored in the memory for sending out image data are replaced by other image data so that the memory adapted to receive image data is filled with affine-transformed image data.
Claim 13
Independent Claim
51 words
A method according to any one of Claims 7 to 10, wherein the processing of the image data effected between the two memories is a coordinate conversion which is effected by the affine transformation or inverse affine transformation to perform rotation, expansion or reduction, deformation or the like of the image.
Claim 14
Independent Claim
173 words
A method according to any one of Claims 7 to 11, wherein prior to subjecting the image data to the affine transformation between the memories the address control of each of which is performed in accordance with the multidimensional array, the initial setting upon performing the processing of the image data between both memories is effected by finding out the degree of overlapping between the two-dimensional address area of the memory, in which the image data before the affine transformation thereof are stored, and the two-dimensional address area of the memory in which the affine-transformed image data are stored through the inverse affine transformation of the addresses of one of the memories, changing the address length or lengths of the the two-dimensional array or arrays of either one or both of the memories so as to optimize the overlapped area, obtaining parameter or parameters corresponding to the address length or lengths and then obtaining an affine coefficient by which the addresses of both memories are corresponded to each other through inverse affine transformation.
Claim 15
Independent Claim
248 words
A system for processing data on an original picture, which data are stored as image data in a memory having a large capacity and a relatively low access speed, said method including (a) dividing at least one group of the data into a plurality of data portions on the basis of a processable size between two memories capable of performing writing and reading at high speeds, (b) reading out the image data in each data portion from the low-speed memory to perform at least one type of image processing on the read-out image data between the high-speed memories, (c) storing the thus-processed image data again in the low-speed memory, and then (d) performing the above steps (a) through (c) repeatedly on the entirety of the data on the original picture so as to store the processed data on the original picture in the large-capacity and low-speed memory, characterized in that the system is equipped with at least two image memory devices, which are employed in the course of the image processings (a) through (d), can perform reading and writing at high speeds and are address-controlled in accordance with multidimensional arrays, and address control means which permits the processing of the image data between the two memory devices while changing the address lengths of the respective dimensions of at least either one of the two memory devices in such a way that the number of divisions of the image is reduced upon performing the processing of the image data.
Claim 16
Independent Claim
248 words
A system for processing data on an original picture, which data are stored as image data in a memory having a large capacity and a relatively low access speed, said method including (a) dividing at least one group of the data into a plurality of data portions on the basis of a processable size between two memories capable of performing writing and reading at high speeds, (b) reading out the image data in each data portion from the low-speed memory to perform at least one type of image processing on the read-out image data between the high-speed memories, (c) storing the thus-processed image data again in the low-speed memory, and then (d) performing the above steps (a) through (c) repeatedly on the entirety of the data on the original picture so as to store the processed data on the original picture in the large-capacity and low-speed memory, characterized in that the system is equipped with at least two image memory devices, which are employed in the course of the image processings (a) through (d), can perform reading and writing at high speeds and are address-controlled in accordance with multidimensional arrays, and address control means which permits the processing of the image data between the two memory devices while changing the address lengths of the respective dimensions of at least either one of the two memory devices in such a way that the number of divisions of the image is reduced upon performing the processing of the image data.
Claim 17
Dependent Claim
56 words
A system according to Claim 13, wherein the memory device the address control of which is effected in accordance with the multidimensional array is equipped, before an address designation circuit for designating the addresses of the memory directly by numerical address signals, with address modification means which modifies multidimensionally-arrayed address signals to the numerical address signals.
Claim 18
Dependent Claim
28 words
A system according to Claim 14, wherein the address modification means is composed of a central processing unit (CPU) for controlling the processing of the image data centrally.
Claim 19
Dependent Claim
119 words
A memory device the control of addresses of which is performed in accordance with a two-dimensional array of numerical addresses of n bits, characterized in that before the address input terminal of the memory, there is additionally provided an address modification circuit adapted to produce numerical address signals of n bits, in each of which signals the sizes of the array elements in the x-address and y-address are different, from x-addresses of a two-dimensional image in which one array elements of arrayed addresses are expressed by bits, y-addresses of the two-dimensional image in which the other array elements are expressed by m bits, where (n-ℓ) ≤ m, and parameter signals input based on the size of the two-dimensional image.
Claim 20
Dependent Claim
119 words
A memory device the control of addresses of which is performed in accordance with a two-dimensional array of numerical addresses of n bits, characterized in that before the address input terminal of the memory, there is additionally provided an address modification circuit adapted to produce numerical address signals of n bits, in each of which signals the sizes of the array elements in the x-address and y-address are different, from x-addresses of a two-dimensional image in which one array elements of arrayed addresses are expressed by bits, y-addresses of the two-dimensional image in which the other array elements are expressed by m bits, where (n-ℓ) ≤ m, and parameter signals input based on the size of the two-dimensional image.
Claim 21
Dependent Claim
36 words
A memory device according to Claim 16, wherein the address modification circuit is composed of a circuit adapted to determine the sum of the product of a constant and a y-address value and an x-address value.
Claim 22
Dependent Claim
36 words
A memory device according to Claim 16, wherein the address modification circuit is composed of a circuit adapted to determine the sum of the product of a constant and an x-address value and a y-address value.
Claim 23
Dependent Claim
63 words
A memory device as claimed in Claim 16, wherein the address modification circuit is composed of a circuit capable of allocating bit by bit x-addresses and y-addresses, both of which are expressed in binary numbers, to memory addresses also expressed in binary numbers while making the way of allocation variable in accordance with the maximum x-address and maximum y-address of the two-dimensional image.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.