VCO centering circuit

Claim 2

An improved phase lock loop circuit arrangement comprising: an oscillator means having an input terminal and an output terminal; a phase detector means coupled to the output terminal; a frequency detector means coupled to said output terminal; a multiplexor means coupled to the frequency detector means and the phase detector means; a charge pump means coupled to the multiplexor; an amplifier means coupled to the charge pump; an adjustable centering circuit means coupled to the charge pump and operable for providing a control signal for centering the frequency of the oscillator means; a summing means operable for summing electrical signals outputted from the adjustable centering circuit means and the amplifier means to form a single signal for driving the oscillator means; and an enabling signal means operable for periodically enabling the multiplexor means to allow the passing of signals from the frequency detector means only and for periodically enabling the adjustable centering circuit means to adjust its output signal until the frequency of the oscillator means falls within a predetermined range.

Claim 3

The phase lock loop of Claim 1 further including means operable for periodically generating a control signal indicating that the frequency of the oscillator means is within the predetermined range.

Claim 4

The phase lock loop of Claim 2 wherein the means for periodically generating the control signal includes an energy detector having an input coupled to the phase detector means; a phase lock loop detector having an input coupled to the charge pump means; and an "AND" circuit means connected with the energy detector and the phase lock loop detector.

Claim 5

The phase lock loop of Claim 1 wherein the adjustable centering circuit means includes: a D/A converter, a counting means being coupled to the converter; first means being coupled to the counter and operable to determine the range over which the counter is active; clock means operable for stepping the counter; and second means operable for controlling the counter.

Claim 6

The phase lock loop of Claim 4 wherein the first means includes a pair of comparator means one of which being operable to define the top limit of the range and the other being operable to define the bottom limit of the range and a pair of "AND" circuits one of each being coupled to an output from the comparator means; said "AND" circuits being operable to combine the signals generated from the comparators with a control signal to provide signals indicating the direction for stepping the counter.

Claim 7

The phase lock loop of Claim 4 wherein the clock means includes a low frequency oscillator; and an "AND" circuit connected to the low frequency oscillator.

Claim 8

The phase lock loop of Claim 4 wherein the second means includes a latch means; and a single shot circuit connected to the latch means.

Claim 9

In a phase lock loop circuit arrangement having a voltage control oscillator with a center operating frequency f and output frequency f , a reference means that provides a reference frequency f , a phase comparator means connected to the reference means and the voltage control oscillator and operable for providing an error signal representative of the difference between f and f o , the improvement comprising: a D/A converter means coupled to the VCO; a counting means connected to the D/A converter means and operable for storing a count representative of a current being needed for driving the VCO so that the output frequency f o is being centered; a first means for presetting the counter; a second means for incrementing the counter; a third means for decrementing the counter; means operable for setting a predetermined voltage range within which an error voltage must fall whenever f o = f c and for comparing the error voltage with the predetermined range and to apply range signals to the second and third means if the error voltage falls outside of the predetermined range; and control means operable for providing control signals for enabling the first, second and third means.

Claim 10

In a phase lock loop circuit arrangement having a voltage control oscillator with a center operating frequency f and output frequency f , a reference means that provides a reference frequency f , a phase comparator means connected to the reference means and the voltage control oscillator and operable for providing an error signal representative of the difference between f and f o , the improvement comprising: a D/A converter means coupled to the VCO; a counting means connected to the D/A converter means and operable for storing a count representative of a current being needed for driving the VCO so that the output frequency f o is being centered; a first means for presetting the counter; a second means for incrementing the counter; a third means for decrementing the counter; means operable for setting a predetermined voltage range within which an error voltage must fall whenever f o = f c and for comparing the error voltage with the predetermined range and to apply range signals to the second and third means if the error voltage falls outside of the predetermined range; and control means operable for providing control signals for enabling the first, second and third means.

Claim 11

In a phase lock loop circuit arrangement having a voltage control oscillator with a center operating frequency f and output frequency f , reference means that provides a reference frequency f , a phase comparator means connected to the reference means and the voltage controlled oscillator and operable for providing an error signal representative of the differences between f and f o , a method for biasing the VCO so that f 0 = f c comprising the steps of: (a) providing a local crystal oscillator for periodically driving the VCO; (b) providing a biasing means with a count for periodically supplying a bias current to the VCO; (c) providing a reference window representative of a voltage range available for driving the VCO; (d) forcing the VCO with an output signal from the crystal oscillator until f o is substantially equivalent to the local crystal frequency. (e) monitoring the output signal of the VCO; (f) comparing the signal with the reference window; (g) adjusting the bias current if the signal falls outside of the reference window; and repeating steps (e) - (g) until the output signal falls within the reference window.

Claim 12

In a phase lock loop circuit arrangement having a voltage control oscillator with a center operating frequency f and output frequency f , reference means that provides a reference frequency f , a phase comparator means connected to the reference means and the voltage controlled oscillator and operable for providing an error signal representative of the differences between f and f o , a method for biasing the VCO so that f 0 = f c comprising the steps of: (a) providing a local crystal oscillator for periodically driving the VCO; (b) providing a biasing means with a count for periodically supplying a bias current to the VCO; (c) providing a reference window representative of a voltage range available for driving the VCO; (d) forcing the VCO with an output signal from the crystal oscillator until f o is substantially equivalent to the local crystal frequency. (e) monitoring the output signal of the VCO; (f) comparing the signal with the reference window; (g) adjusting the bias current if the signal falls outside of the reference window; and repeating steps (e) - (g) until the output signal falls within the reference window.

Claim 13

The method of Claim 9 further including the steps of locking the biasing means with the count that causes the output signal to fall within the predetermined range; and providing a signal indicating that the adjustment is completed.