A soft error protection circuit for a latch

Claim 2

A soft error protection circuit for a latch having a first node (8') and a second node (8) which are respectively connected to a charging source (10), said first node (8') being selectively charged at least during a write interval, to represent a stored, first binary logic state for said storage cell, characterized by an insulated gate field effect capacitor (18) having a diffusion electrode (20) connected to said second node (8) and having a gate electrode (22), for selectively loading said second node (8) with an additional capacitance; an inverter circuit (24) having an input (26) connected to said second node (8) and an output (28) connected to said gate electrode (22) of said capacitor (18), for applying a capacitance enhancing bias to said gate electrode (22) in at least a read interval following said write interval, when said first binary logic state has been stored in said latch (6), to apply said additional capacitance to said second node (8); said charging source (10) supplying charge to both said first node (8') and said second node (8) at least following a soft error event which has caused said first node (8') to become at least partially discharged during said read interval; said additional capacitance (18) applied to said second node (8) preventing said second node (8) from recharging as fast as said first node (8') following said soft error event, by sinking a portion of the charge supplied from said charging source (10) to said second node (8); whereby said first node (8') will resume its previously charged condition, thereby preserving the stored logic state of said storage cell (6) following a soft error event.

Claim 3

The circuit as claimed in claim 1, characterized by said latch (6) being connected to a first binary state input device which is enabled by a write-enable input (WE 14), said first node (8') being selectively charged at least during a write interval when said write-enable (WE 14) input is on, to represent a stored, first binary logic state for said latch, and said circuit further comprising

Claim 4

a transfer field effect transistor device (30) having its source-drain path connected between said output (28) of said inverter (24) and said gate electrode (22) of said capacitor (18), and having its gate connected to said write-enable input (WE 14), for applying a capacitance enhancing bias produced by said output (28) of said inverter (24) to said gate electrode (22) of said capacitor (18) in said write interval when said write-enable input (WE 14) is on, to apply said additional capacitance to said second node (8).

Claim 5

a transfer field effect transistor device (30) having its source-drain path connected between said output (28) of said inverter (24) and said gate electrode (22) of said capacitor (18), and having its gate connected to said write-enable input (WE 14), for applying a capacitance enhancing bias produced by said output (28) of said inverter (24) to said gate electrode (22) of said capacitor (18) in said write interval when said write-enable input (WE 14) is on, to apply said additional capacitance to said second node (8).

Claim 6

The circuit as claimed in claim 2, characterized by a ballast capacitor (32) being connected between said gate (22) of said insulated gate field effect capacitor (18) and said transfer field effect transistor (30), for maintaining said capacitance enhancing bias on said gate electrode (22) of said insulated gate field effect capacitor (18) during a read interval following said write interval, when said write-enable input (WE 14) is off.

Claim 7

The circuit as claimed in claim 1, characterized by an insulated gate, field effect capacitor (18) having a diffusion electrode (20) connected to said second node (8) and having a gate electrode (22) for selectively loading said second node (8) with an additional capacitance; an inverter circuit (24) having an input (26) connected to said second node (8) and an output (28) connected to said gate electrode (22) of said capacitor, for applying a capacitance enhancing bias to said gate electrode (22) in at least a read interval following said write interval, when said first binary logic state has been stored in said latch (6), to apply said additional capacitance .to said second node (8); said charging source (10) applying charge to both said first node (8') and said second node (8) at least following a soft error event which has caused said first node (8') to become at least partially discharged during said read interval; said additional capacitance (18) applied to said second node (8) preventing said second node (8) from recharging as fast as said first node (8') following said soft error event, by sinking a portion of the charge supplied from said charging source (10) to said second node (8), said first node (8') resuming its previously charged condition; said second node (8) being selectively charged at least during a second write interval, to represent a stored, second binary logic state for said latch; a second insulated gate, field effect capacitor (18') having a diffusion electrode (20') connected to said first node (8') and having a second gate electrode (22'), for selectively loading said first node (8') with a second additional capacitance; a second inverter circuit (24') having an input (26') connected to said first node (8') and an output (28') connected to said second gate electrode (22') of said second capacitor (18'), for applying a capacitance enhancing bias to said second gate electrode (22') in at least a second read interval following said second write interval, when said second binary logic state has been stored in said latch (6), to apply said second additional capacitance to said first node (8'); said charging source (10) supplying charge to both said second node (8) and said first node (8') at least following a second soft error event which has caused said second node (8) become at least partially discharged during said second read interval; said second additional capacitance (18') applied to said first node (8') preventing said first node (8') from recharging as fast as said second node (8) following said second soft error event by sinking a portion of the charge supplied from said charging source (10) to said first node (8'), said second node (8) resuming its previously charged condition; whereby, the stored logic state of said latch (6) is preserved following a soft error event

Claim 8

The circuit as claimed in claim 4, characterized by said latch (6) being connected to a first binary state input device which is enabled by a write-enable input (WE 14), said first node (8') being selectively charged at least during a first write interval when said write-enable input (WE 14) is on, to represent a stored, first binary logic state for said latch, and said circuit further comprising a first insulated gate field effect capacitor (18) having a diffusion electrode (20) connected to said second node (8) and having a gate electrode (22), for selectively loading said second node (8) with a first additional capacitance when its gate is biased with respect to said diffusion electrode (20); a first inverter (24) having an input (26) connected to said second node (8) and an output (28); a first transfer field effect transistor device (30) having its source-drain path connected between said output (28) of said inverter (24) and said gate electrode (22) of said first capacitor (18), and having its gate connected to said write-enable input (WE 14), for applying a capacitance enhancing bias produced by said output (28) of said first inverter (24) to said gate electrode (22) of said first capacitor (18) in said write interval when said write-enable input (WE 14) is on, to apply said first additional capacitance to said second node (8); said charging source (10) supplying charge to both said first node (8') and said second node (8) at least following a soft error event which has caused said first node (8') to become at least partially discharged during a first read interval following said first write interval; said first additional capacitance (18) applied to said second node (8) preventing said second node (8) from recharging as fast as said first node (8') following said soft error event by sinking a portion of the charge supplied from said charging source (10) to said second node (8), so that thereby said first node (8') will resume its previously charged condition; said latch (6) being connected to a second binary state input device which is enabled by a write-enable input (WE 14), said second node (8) being selectively charged at least during a second write interval when said write-enable input is on, to represent a stored, second binary logic state for said latch; a second insulated gate field effect capacitor (18') having a diffusion electrode (20') connected to said first node (8') and having a gate electrode (22), for selectively loading said first node (8') with a second additional capacitance when its gate (22') is biased with respect to its diffusion electrode (20'); a second inverter (24') having an input (26') connected to said first node (8') and an output (28'); a second transfer field effect transistor device (30') having its source-drain path connected between said output (28') of said second inverter (24') and said gate electrode (22') of said second insulated gate field effect capacitor (18'), and having its gate (22') connected to said write-enable input, for applying a capacitance enhancing bias produced by said output (28') of said second inverter (24') to said gate electrode (22') of said second insulated gate field effect capacitor (18') in said second write interval when said write-enable input (WE 1 4) is on, to apply said second additional capacitance to said first node (8'); said charging source (10) supplying charge to both said second node (8) and said first node (8') at least following a soft error event which has caused said second node (8) to become at least partially discharged during a second read interval following said second write interval; said second additional capacitance (18') applied to said first node (8') preventing said first node (8') from recharging as fast as said second node (8) following said soft error event, by sinking a portion of the charge supplied from said charging source (10) to said first node (8'), so that thereby said second node (8) will resume its previously charged condition; whereby the stored logic state of said latch (6) is preserved following a soft error event

Claim 9

The circuit as claimed in claim 5, characterized by a first ballast capacitor (32) connected between said gate (22) of said first insulated gate field effect capacitor (18) and said first transfer field effect transistor (30), for maintaining said capacitance enhancing bias on said gate electrode (22) of said first insulated gate field effect capacitor (18) during said first read interval following said first write interval, when said write-enable input (WE 1 4) is off; a second ballast capacitor (32') connected between said gate (22') of said second insulated gate field effect capacitor (18') and said second transfer field effect transistor (30'), for maintaining said capacitance enhancing bias on said gate electrode (22') of said second insulated gate field effect capacitor (18') during said second read interval following said second write interval, when said write-enable input (WE 14) is off.