EP0189576A2
Expired / Lapsed
EP
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Multiple pixel mapped video memory system
Assignee: Texas Instruments Inc
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Filing: 1985-12-17
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Granted: —
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Expires: 2005-12-17
Abstract
Abstract A semiconductor memory is comprised of four arrays (10), (12), (14) and (16) that have the memory elements therein arranged in accordance with pixel positions on a video display; i.e., bit-mapped. The memory arrays have associated shift registers (34), (36), (38) and (40) which have data loaded in parallel and output in a serial format to the display. Each of the shift registers can be connected in a circulating fashion or a shift register of adjacent arrays can be cascaded. Switches (56), (58), (60) and (62) are provided for configuring the shift registers for either circulation or cascading of data. In the circulating mode, the input and output of the shift registers is multiplexed on one pin whereas in the cascaded configuration, one array receives a dedicated serial input and the other array in the cascaded pair outputs the serial output on a dedicated pin. A circuit used for inhibiting data transfer to addressed memory locations in the arrays includes an arbitration circuit (68) that distinguishes between separate inhibit signal inputs on dedicated CAS terminals and multiplexed inhibit signals on the input of an I/O buffer (66). The arbitration circuit (68) controls the enable circuits (64) for transferring data from the I/O buffer (66) to memory arrays (10), (12), (14), and (16). Separate inhibit signals allow multiple arrays to share common row and column decoders and maintain separate read/write capability. In one embodiment, a tap latch (88) is provided on the output of each of the shift bits in the shift register (86) for determining the output therefrom. The tap latch (88) stores a tap decode signal which is decoded from a tap address by the column decoder (30). The column decoder (30) also decodes the column address in the random mode. The tap decode signal selects any of the shift bits in the shift register (86). Another feature is the use of transfer gates (54) disposed between the memory arrays and the associated shift registers. A control circuit (69) is provided for receiving an external transfer signal and transferring the data between the arrays and the associated shift registers. The shift registers are clocked in response to receiving an external shift clock signal to serially output data therefrom. A delay circuit (292) is provided for delaying shifting of data for a predetermined duration to ensure that a complete transfer of data has been effected. Transfer of data is inhibited until the occurrence of the XBOOT signal by circuit (296) to provide for early occurrence of the transfer signal. Data access is maintained by a delay circuit (330) to accommodate late occurrence of the transfer signal by delaying the internal row address strobe.
Inventors
- 👤 Raymond Pinkham
- 👤 Fredrick A. Valente
- 👤 Jerry R. Vanaken
- 👤 Daniel F. Anderson
- 👤 Karl M. Guttag
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 01:33
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/84; G11C29/848; G09; G09G; G09G5/00; G09G5/36; G09G5/39; G11C7/00; G11C7/10; G11C7/1006; G11C7/1075; G11C8/00; G11C8/12; G09G2360/00; G09G2360/12; G09G2360/123; G09G2360/126
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
262 words
A semiconductor memory for storing pixel information for a video display, comprising: a first memory array having a plurality of memory elements arranged in rows and columns and associated with a predetermined pixel locations in the display; a second memory array having a plurality of memory elements arranged in rows and columns and associated with predetermined pixel locations on the display said first and second memory arrays being identical; row decode means for receiving a row address and selecting one of the rows of memory elements in both said first and second memory arrays; first serial access means for storing data from the selected memory elements of said first memory array in a serial format; said second serial access means for storing data from selected memory elements of said second memory array in a serial format; said first and second serial access means having a separate serial input and a separate serial output and controlled from an external source to serially shift data therethrough; transfer means for transferring data from the selected memory elements at said first and second array to the respective one of said first and second serial access means or from said serial access means to the selected memory elements in said first and second array; and means for configuring said first and second access means to each circulate data from the serial output to serial input thereof or to cascade said first and second serial access means with the serial output of said first serial access means connected to the serial input of said second serial access means.
Claim 2
Dependent Claim
262 words
A semiconductor memory for storing pixel information for a video display, comprising: a first memory array having a plurality of memory elements arranged in rows and columns and associated with a predetermined pixel locations in the display; a second memory array having a plurality of memory elements arranged in rows and columns and associated with predetermined pixel locations on the display said first and second memory arrays being identical; row decode means for receiving a row address and selecting one of the rows of memory elements in both said first and second memory arrays; first serial access means for storing data from the selected memory elements of said first memory array in a serial format; said second serial access means for storing data from selected memory elements of said second memory array in a serial format; said first and second serial access means having a separate serial input and a separate serial output and controlled from an external source to serially shift data therethrough; transfer means for transferring data from the selected memory elements at said first and second array to the respective one of said first and second serial access means or from said serial access means to the selected memory elements in said first and second array; and means for configuring said first and second access means to each circulate data from the serial output to serial input thereof or to cascade said first and second serial access means with the serial output of said first serial access means connected to the serial input of said second serial access means.
Claim 3
Dependent Claim
65 words
The semiconductor memory of Claim 1 and further comprising: column decode means for receiving a column address and selecting one of the columns of memory elements in both said first and second memory arrays; and random read/write means for inputting data to the selected one of the memory elements in both said first and second memory arrays as defined by the row and column addresses.
Claim 4
Dependent Claim
73 words
The semiconductor memory of Claim 1 wherein said first and second serial access means comprise serial shift registers having a plurality of shift bits equal in number to the number of columns in the respective one of said first and second memory arrays, each of the selected memory elements in the respective one of said first and second memory arrays transferred to the respective one of said shift bits by said transfer means.
Claim 5
Dependent Claim
142 words
The semiconductor memory of Claim 1 and further comprising first and second interface means for interfacing between said first and second access means and external peripheral circuitry with respect to the memory, said means for configuring further comprising means for multiplexing the operation of said first and second access means when configured to circulate data such that said first interface means associated with said first access means and multiplexed to either input serial data to said first access means or receive serial data output therefrom and said second interface means associated with-said second access means and multiplexed to either input-serial data thereto or received serial output data therefrom, said first interface means inputting serial data to said first serial access means when configured in the cascaded mode and said second interface means receiving serial output data from said second serial access means.
Claim 6
Dependent Claim
130 words
The semiconductor memory of Claim 1 wherein said configuring means comprises first switch means having first and second positions, said first position operable to connect the serial output of said first access means to the serial input thereof, said second position operable to connect the serial output of said first access means to the serial input of said second access means; and second switch means having first and second positions, said first position operable to connect the output of said serial access means to the serial input thereof, said second position operable to inhibit circulation of data from the serial output of said second serial access means to the serial input thereof; and means for configuring said first and second switches in either said first position or said second position.
Claim 7
Dependent Claim
54 words
The semiconductor memory of Claim 5 and further comprising: first interface means for interfacing between peripheral circuitry external to the semiconductor memory and the serial input of said first access means; and second interface means for interfacing between the circuitry external to the semiconductor memory and the serial output of said second access means.
Claim 8
Dependent Claim
33 words
The semiconductor memory of Claim 5 wherein said first and second switches are programmed in either said first state or said second state as a mask option during fabrication of the semiconductor memory.
Claim 9
Dependent Claim
329 words
8 . A semiconductor memory for storing pixel information for a video display, comprising: a first memory array having a plurality of memory elements arranged in rows and columns and associated with predetermined pixel locations ,on the display; a second memory having a plurality of memory elements arranged in rows and columns and associated with predetermined pixel locations on the display said first and second memory arrays being identical; row access means for receiving a row address and simultaneously selecting one of the rows of memory elements in both said first and second memory arrays; first serial access means-for storing the data from the selected memory elements of said first memory array in a serial format and arranged in the order of the columns; second serial shifting means for storing data from the selected memory elements of said second memory array in a serial format according to the order of the columns therein; said first and second shifting means having a serial input and a serial output and shifting therein controlled from an external source to serially shift data therethrough; first multiplexing means for multiplexing the serial input and output of said first shifting means with an external port that interfaces circuitry external to the semiconductor memory with the internal operation thereof; said multiplexing means for connecting either the serial input or output of said second shifting means with a second interface port that interfaces circuitry external to the semiconductor memory with functions internal thereof; said first and second multiplexing means operated by a single signal from an external source with respect to the semiconductor memory such that either both the serial inputs or both the serial outputs can be selected; and transfer means for transferring data from the selected memory elements in said first and second array to the respective one of said first and second shifting means or transferring data from said first and second shifting means to the respective one of said first and second arrays.
Claim 10
Dependent Claim
329 words
8 . A semiconductor memory for storing pixel information for a video display, comprising: a first memory array having a plurality of memory elements arranged in rows and columns and associated with predetermined pixel locations ,on the display; a second memory having a plurality of memory elements arranged in rows and columns and associated with predetermined pixel locations on the display said first and second memory arrays being identical; row access means for receiving a row address and simultaneously selecting one of the rows of memory elements in both said first and second memory arrays; first serial access means-for storing the data from the selected memory elements of said first memory array in a serial format and arranged in the order of the columns; second serial shifting means for storing data from the selected memory elements of said second memory array in a serial format according to the order of the columns therein; said first and second shifting means having a serial input and a serial output and shifting therein controlled from an external source to serially shift data therethrough; first multiplexing means for multiplexing the serial input and output of said first shifting means with an external port that interfaces circuitry external to the semiconductor memory with the internal operation thereof; said multiplexing means for connecting either the serial input or output of said second shifting means with a second interface port that interfaces circuitry external to the semiconductor memory with functions internal thereof; said first and second multiplexing means operated by a single signal from an external source with respect to the semiconductor memory such that either both the serial inputs or both the serial outputs can be selected; and transfer means for transferring data from the selected memory elements in said first and second array to the respective one of said first and second shifting means or transferring data from said first and second shifting means to the respective one of said first and second arrays.
Claim 11
Dependent Claim
59 words
The semiconductor memory of Claim 8 wherein said shifting means comprises serial shift registers having a plurality of shift bits therein, the input of each of the shift bits associated with one of the columns in the respective one of said first and second arrays for receiving data therefrom or transferring data thereto in response to said transfer means.
Claim 12
Dependent Claim
128 words
A semiconductor memory, comprising: a plurality of memory arrays each having an equal number of memory elements arranged in rows and columns; common decode means for receiving a row address and a column address and selecting one of the memory elements in each said arrays, each of said selected memory elements having a common row and column location; output means associated with each of said arrays for transferring data to said selected memory elements or extracting data from said selected memory elements; and inhibiting means for inhibiting transfer of data to selected ones of said arrays and subsequent storage in the associated one of said selected memory elements such that data prestored in said selected memory elements associated with the inhibited ones of said arrays is not disturbed.
Claim 13
Dependent Claim
128 words
A semiconductor memory, comprising: a plurality of memory arrays each having an equal number of memory elements arranged in rows and columns; common decode means for receiving a row address and a column address and selecting one of the memory elements in each said arrays, each of said selected memory elements having a common row and column location; output means associated with each of said arrays for transferring data to said selected memory elements or extracting data from said selected memory elements; and inhibiting means for inhibiting transfer of data to selected ones of said arrays and subsequent storage in the associated one of said selected memory elements such that data prestored in said selected memory elements associated with the inhibited ones of said arrays is not disturbed.
Claim 14
Dependent Claim
72 words
The memory of Claim 10wherein said common decode means comprises: common row decode means for receiving the row address and selecting one of the rows of memory elements in each of said arrays; and common column decode means for receiving the column address and selecting one of the columns of memory elements in each of said arrays such that the memory element selected in each of said arrays has a common location.
Claim 15
Dependent Claim
62 words
The semiconductor memory of Claim 10 wherein the column address is preceded by the row address, said common decode means comprising means for latching the row address for selection of a row of memory elements and means for latching the column address after the row address is latched such that subsequent column addresses can be latched for a given batched row address.
Claim 16
Dependent Claim
89 words
The semiconductor memory of Claim 12 wherein said inhibiting means comprises: means for receiving inhibiting signals associated with each of said arrays, said inhibiting signals present only for the ones of said arrays to be inhibited; means for controlling said output means in response to receiving said inhibiting signals such that transfer of data to the selected ones of said memory elements in said arrays associated with the received ones of said inhibiting signals is prevented through inhibition of the one of said output means associated with said array.
Claim 17
Dependent Claim
40 words
The semiconductor memory of Claim 13 and further comprising means for storing the received ones of said inhibiting signals after reception thereof, said output means associated with stored ones of said inhibiting signals controlled to inhibit transfer of data therethrough.
Claim 18
Dependent Claim
30 words
. 15. The memory of Claim 14 wherein said inhibiting signals precede the row address such that altering of said inhibiting signals requires generation of new row and column addresses.
Claim 19
Dependent Claim
63 words
The semiconductor memory of Claim 14 wherein the row address precedes the reception of said inhibiting signals and said inhibiting signals precede the column address such that said inhibiting signals can be altered after reception of the row address and the ones of said arrays that are inhibited can be changed prior to generating a new column address for a given row address.
Claim 20
Dependent Claim
32 words
The semiconductor memory of Claim 14wherein said inhibiting signals are generated from an external source for the duration of time that data transfer is inhibited through inhibited ones of said output means.
Claim 21
Dependent Claim
86 words
The semiconductor memory of Claim 10wherein said output means comprises input/output buffers associated with each of said arrays, each of said buffers .having a single output port for interfacing to an external data source, a data input port for transferring data from said output port to the associated one of said arrays and a data output port for transferring data from the associated one of said arrays to said output port, said data input port controlled by said inhibiting means to inhibit transfer of data therethrough.
Claim 22
Dependent Claim
226 words
A semiconductor memory, comprising: a plurality of memory arrays each having an equal number of memory elements arranged in rows and columns; a common row decoder for receiving the row address and selecting one of the rows in each of said arrays corresponding to the received row address; a common column decoder for receiving a column address and selecting one of the columns in each of said arrays corresponding to the received column address, selection of a row and column in each of said arrays defining the location of the memory elements to be accessed in each of said arrays; an input/output buffer associated with each of said arrays and each having: an interface terminal for receiving data from and transferring data to an external source, a data-in port for transferring data to the accessed memory element in the associated one of said arrays, and a data-out port for receiving data from the accessed memory element in the associated one of said arrays; means for receiving inhibiting signals from an external source, each of said arrays and associated buffers having one of said inhibiting signals associated therewith; and means for inhibiting data transfer through the data-in port on one of said buffers associated with said received inhibiting signals such that data stored in the accessed one of the memory elements in said associated array remains unchanged.
Claim 23
Dependent Claim
226 words
A semiconductor memory, comprising: a plurality of memory arrays each having an equal number of memory elements arranged in rows and columns; a common row decoder for receiving the row address and selecting one of the rows in each of said arrays corresponding to the received row address; a common column decoder for receiving a column address and selecting one of the columns in each of said arrays corresponding to the received column address, selection of a row and column in each of said arrays defining the location of the memory elements to be accessed in each of said arrays; an input/output buffer associated with each of said arrays and each having: an interface terminal for receiving data from and transferring data to an external source, a data-in port for transferring data to the accessed memory element in the associated one of said arrays, and a data-out port for receiving data from the accessed memory element in the associated one of said arrays; means for receiving inhibiting signals from an external source, each of said arrays and associated buffers having one of said inhibiting signals associated therewith; and means for inhibiting data transfer through the data-in port on one of said buffers associated with said received inhibiting signals such that data stored in the accessed one of the memory elements in said associated array remains unchanged.
Claim 24
Dependent Claim
31 words
The semiconductor memory of Claim 19 wherein said means for receiving comprises means for storing said inhibiting signals after reception thereof, storage of said inhibiting signals controlling said means for inhibiting.
Claim 25
Dependent Claim
51 words
The semiconductor memory of Claim 20 and further comprising means for multiplexing the interface terminals of said input/output buffers to receive the associated ones of said inhibiting signals thereon for input to said storage means, said multiplexing means operable to receive said inhibiting signals before data transfer on the interface terminals.
Claim 26
Dependent Claim
43 words
The semiconductor memory of Claim 19 wherein said means for receiving comprises a dedicated terminal associated with each of said inhibiting signals, said inhibiting signals present for the duration of time that the ones of said arrays associated therewith are to be inhibited.
References Cited (Backward Citations)
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