EP0198698A2
Expired / Lapsed
EP
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Integrated circuit device having strip line structure therein
Assignee: Fujitsu Ltd
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Filing: 1986-04-14
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Granted: —
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Expires: 2006-04-14
Abstract
Abstract @ An integrated circuit device (1) includes at least one semiconductor chip (3) having a plurality of circuit elements; a package (21 to 24) enclosing the semiconductor chip with a hermetic seal; and a strip line unit (15-2, 11-lb, 11-2, 20 and 23 : 15-1, 11-1, 11-2, 11-3, 12-1 and 20) for connecting the circuit elements in the semiconductor chip to circuitry outside the package. The stripline unit has a microstrip line structure and a triplate strip line structure serial-connected to the microstrip line structure and connecting the outside circuits. The triplate strip line structure has a characteristic impedance equal to that of the microstrip line structure so that the strip line unit satisfies the required impedance matching. A center of the conductive layer strip line of the triplate strip line structure has a smaller width than that of a microstrip line of the microstrip line structure to have a predetermined impedance so that the triplate strip line structure has a same characteristic impedance as that of the microstrip line structure.
Inventors
- 👤 Akira Miyauchi
- 👤 Hiroshi Nishimoto
- 👤 Tadashi Fujimiso 1261 Okiyama
- 👤 Hiroo Shirahatadaijutaku 4-203 Kitasagami
- 👤 Masahiro Sugimoto
- 👤 Haruo Tamada
- 👤 Shinji Emori
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 04:17
CPC Classifications
H; H10; H10W; H10W44/00; H10W44/601; H01; H01P; H01P5/00; H01P5/02; H01P5/022; H01P5/028; H01P5/08; H10W44/20; H05; H05K; H05K1/00; H05K1/02; H05K1/0213; H05K1/0237; H05K3/00; H05K3/30; H05K3/32; H05K3/325; H10W44/203; H10W44/209; H10W72/00; H10W72/50; H10W72/541; H10W72/5449; H10W90/00; H10W90/701; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
113 words
An integrated circuit device comprising: at least one semiconductor chip (3) having a plurality of circuit elements; package means (21 to 24) enclosing said semiconductor chip with a hermetic seal; and strip line means (15-2, 11-lb, 11-2, 20 and 23 : 15-1, 11-1, 11-2, 11-3, 12-1 and 20) for connecting said circuit elements in said semiconductor chip to circuits outside of said package means, having a microstrip line structure and a triplate strip line structure serial-connected to said microstrip line structure and connecting said outside circuit, said triplate strip line structure having a characteristic impedance equal to that of said microstrip line structure so that said strip line means satisfies said impedance matching.
Claim 2
Dependent Claim
113 words
An integrated circuit device comprising: at least one semiconductor chip (3) having a plurality of circuit elements; package means (21 to 24) enclosing said semiconductor chip with a hermetic seal; and strip line means (15-2, 11-lb, 11-2, 20 and 23 : 15-1, 11-1, 11-2, 11-3, 12-1 and 20) for connecting said circuit elements in said semiconductor chip to circuits outside of said package means, having a microstrip line structure and a triplate strip line structure serial-connected to said microstrip line structure and connecting said outside circuit, said triplate strip line structure having a characteristic impedance equal to that of said microstrip line structure so that said strip line means satisfies said impedance matching.
Claim 3
Dependent Claim
125 words
An integrated circuit device according to claim 1, wherein said strip line means is formed in a stacked layer means (23, 15-2, 11-lb, 11-2a : 15-1, 11-lb, 11-2 ' a, 11-1, 11-2, 11-3) including at least three stacked layers each having an insulation layer and at least one conductive layer formed on a surface of said insulation layer, and a cavity (20) defined by said package means, a microstrip line (15-2a, 15-1) of said microstrip line structure being connected to a center conductive layer strip line (15-2b, 11-3a) of said triplate strip line structure in series, said center conductive layer strip line having a predetermined impedance so that said triplate strip line structure has a same characteristic impedance as that of said microstrip line structure.
Claim 4
Dependent Claim
175 words
An integrated circuit device according to claim 2, wherein said microstrip line structure is formed by said microstrip line (15-2a) having a predetermined thickness and width and facing said cavity (20), an insulation layer (11-lb) of said stacked layer means having a predetermined dielectric constant and said microstrip line being mounted thereon at a plane, and a conductive layer (11-2a) of said stacked layer means mounted on said insulation layer at another plane opposite to said plane, and wherein said triplate strip line structure is formed by said center conductive layer strip line (15-2b) directly connected to said microstrip line, said insulation layer (11-lb) and said center conductive layer strip line being mounted thereon at said one plane, said conductive layer (ll-2a) mounted on said insulation layer at said another plane, another insulation layer (23b) having a predetermined dielectric constant and a predetermined length, formed on said center conductive layer strip line and said insulation layer and forming a part of said package means, and another conductive layer (23a) formed on said another insulation layer,
Claim 5
Dependent Claim
49 words
An integrated circuit device according to claim 3, wherein said microstrip line and said center conductive layer strip line have a same thickness, and said center conductive layer strip line has a smaller width than that of said microstrip line along said length of said another insulation layer (23b).
Claim 6
Dependent Claim
240 words
An integrated circuit device according to claim 2, wherein said microstrip line structure is formed by said microstrip line (15-1) having a predetermined thickness and width and facing said cavity (20), a first insulation layer (11-lb) of said stacked layer means having a predetermined dielectric constant and said microstrip line mounted thereon at a plane, and a first conductive layer (ll-2a) of said stacked layer means mounted on said first insulation layer at another plane opposite to said plane, and wherein said triplate strip line structure is formed by said center conductive layer strip line (11-3a), a second insulation layer (11-2b) of said stacked layer means having a predetermined dielectric constant and said conductive layer strip line is in contact therewith at a plane, a second conductive layer formed on said second insulation layer at another plane, a third insulation layer (11 = 3b) of said stacked layer means having a predetermined dielectric constant and said conductive layer strip line is mounted thereon at a plane, and a third conductive layer (11-4a) formed on said third insulation layer at another plane, said microstrip line being formed on a different insulation layer on which said center conductive layer strip line is formed, and said microstrip line being connected to said center conductive layer strip line through a conductive member embedded in said second and third insulation layers in a direction perpendicular to a plane of said second and third insulation layers.
Claim 7
Dependent Claim
46 words
An integrated circuit device according to claim 5, wherein said first conductive layer (11-2a) of said microstrip line structure and said second conductive layer of said triplate strip line structure are formed as a unit and positioned on a same level in said stacked layer means.
Claim 8
Dependent Claim
40 words
An integrated circuit device according to claim 6, wherein said microstrip line and said center conductive layer strip line have a same thickness, and said center conductive layer strip line has a smaller width than that of said microstrip line.
Claim 9
Dependent Claim
61 words
An integrated circuit device according to claim 2, said stacked layer means is formed as a part of said package means, said semiconductor chip being mounted on a top of insulation layer of said stacked layer means, and said semiconductor chip and said strip line means being enclosed by said package means and said stacked layer means with a hermetic seal.
References Cited (Backward Citations)
No citation records indexed.
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