Method and apparatus for addressing a memory

Claim 3

The method as recited in claim 1 wherein: said method further comprises the step of interpreting a boundary parameter of said array transformation for controlling the generating of said addressing sequences when any one of said displacement parameters causes an address of said sequences to be generated outside a boundary of an array.

Claim 6

The method as recited in claim 3 wherein: said method further comprises the step of interpreting a boundary parameter of said array transformation for controlling the generating of said addressing sequences when any one of said displacement parameters causes said address to be generated outside a boundary of an array.

Claim 9

The method as recited in claim 5 wherein: said method further comprises the step of interpreting a boundary parameter of said array transformation for controlling the generating of said addressing sequences when any one of said displacement parameters causes an address of said sequences to be generated outside a boundary of an array.

Claim 10

The method as recited in claim 6 wherein: said boundary parameter specifies a plurality of modes comprising a wrap-around mode, a zero-fill mode and an ignore boundaries mode.

Claim 13

The method as recited in claim 8 wherein: said method further comprises the step of interpreting a boundary parameter of said array transformation for controlling the generating of said plurality of addresses when said displacement parameter causes an address to be generated outside the boundaries of said array.

Claim 14

The method as recited in claim 9 wherein: said boundary parameter specifies a plurality of modes comprising wrap-around mode, a zero-fill mode and an ignore boundaries mode.

Claim 17

The method as recited in claim 11 wherein: each of said plurality of index generators comprises a row index generator and a column index generator.

Claim 18

The method as recited in claim 11 wherein: said method further comprises the step of interpreting a boundary parameter of said array transformation for controlling the generating of said plurality of addresses when any one of said displacement parameters causes an address to be generated outside the boundaries of said array.

Claim 19

The method as recited in claim 13 wherein: said boundary parameter specifies a plurality of modes comprising a wrap-around mode, a zero-fill mode and an ignore boundaries mode.

Claim 22

The method as recited in claim 15 wherein: said method further comprises the step of interpreting a boundary parameter of said array transformation for controlling the generating of said plurality of addresses when any one of said displacement parameters causes an address to be generated outside the boundaries of said array.

Claim 23

The method as recited in claim 16 wherein: said boundary parameter specifies a plurality of modes comprising a wrap-around mode, a zero-fill mode and an ignore boundaries mode.

Claim 26

The method as recited in claim 18 wherein said steps of generating a plurality of addresses extends to further displacements of said array transformation by the steps of: incrementing a fifth or more of said index generator means with a fifth or more of a corresponding one of said displacement parameters and loading said fifth or more of said index generator means into a corresponding next lower level one of said index generator means and repeating steps (d) through (g) and the present step or steps a plurality of times equal to a correspoonding value of a fifth or more of said length parameters.

Claim 27

The method as recited in claim 18 wherein: said method further comprises the step of interpreting a boundary parameter of said array transformation for controlling the generating of said plurality of addresses when any one of said displacement parameters causes an address to be generated outside the boundaries of said array.

Claim 28

The method as recited in claim 20 wherein: said boundary parameter specifies a plurality of modes comprising a wrap-around mode, a zero-fill mode and an ignore boundaries mode.

Claim 29

The method as recited in claim 21 wherein said wrap-around mode comprises the step of: generating addresses on an opposite side of said array when an array boundary is reached by any one of said plurality of displacement parameters.

Claim 30

The method as recited in claim 21 wherein said zero-fill mode comprises the step of: treating addresses generated outside said array as having zeros stored therein.

Claim 31

The method as recited in claim 21 wherein said ignore boundaries mode comprises the steps of: generating said addressing sequences to proceed through an array in the wrap-around mode ignoring all boundaries until a last address point is reached; and returning to an initial address of said array specified by said initial address parameter.

Claim 32

The method as recited in claim 21 wherein said ignore boundaries mode comprises the steps of: generating said addressing sequences to proceed through an array in the zero-fill mode until a last address point is reached in said array; and continuing to generate address sequences after said last address point.

Claim 35

The method as recited in claim 26 wherein said step of storing data comprises the step of: generating said addressing sequences according to a nested series of a plurality of parameters in said array transformation.

Claim 36

The method as recited, in claim 26 wherein: said method further comprises the step of interpreting a boundary parameter of said array transformation for controlling the generating of said addressing sequences when an address of said sequences may be generated outside a boundary of said array.

Claim 37

The method as recited in claim 28 wherein: said boundary parameter specifies a plurality of modes comprising a wrap-around mode, a zero-fill mode and an ignore boundaries mode.

Claim 38

A digital system comprising: means for interpreting instruction commands; means for performing arithmetic operations based on said commands; means for storing data for said arithmetic operations, said storing means comprising means for generating a plurality of addresses in response to an array transformation for accessing said data; and means for transferring said data between said storing means and said arithmetic operations performing means in accordance with said array transformation.

Claim 39

A digital system comprising: means for interpreting instruction commands; means for performing arithmetic operations based on said commands; means for storing data for said arithmetic operations, said storing means comprising means for generating a plurality of addresses in response to an array transformation for accessing said data; and means for transferring said data between said storing means and said arithmetic operations performing means in accordance with said array transformation.

Claim 40

The digital system as recited in claim 30 wherein: said storing means comprises a port means for generating said plurality of addresses according to said array transformation.

Claim 41

The digital system as recited in claim 30 wherein: said array transformation specifies array addressing in terms of a factored series of nested addressing sequences defined by a plurality of displacement and length parameters.

Claim 42

The digital system as recited in claim 31 wherein: said port means comprises an address generator for generating said plurality of addresses to load or access a data array in said storing means.

Claim 43

A memory comprising: means for storing data; a plurality of read/write port means, said port means comprising means for transferring data to and from a bus means in accordance with addressing sequences specified by an array transformation; and switching network means coupled between said storing means and said port means for routing data transfers between said plurality of storing means and said port means.

Claim 44

A memory comprising: means for storing data; a plurality of read/write port means, said port means comprising means for transferring data to and from a bus means in accordance with addressing sequences specified by an array transformation; and switching network means coupled between said storing means and said port means for routing data transfers between said plurality of storing means and said port means.

Claim 45

The memory as recited in claim 34 wherein: said port means comprises at least two intelligent ports for transferring said data to and from said arithmetic means.

Claim 46

The memory as recited in claim 35 wherein: at least one of said intelligent ports operate in a read mode and at least one of said intelligent ports operates in a write mode.

Claim 47

The memory as recited in claim 34 wherein: said storing means comprises at least one random access memory and at least one read only memory.

Claim 48

The memory as recited in claim 34 wherein: said array transformation comprises a plurality of parameters for the generation of said addressing sequences for transferring a data array to or from said memory, said array comprises a vector, a matrix or a block of data.

Claim 49

An intelligent memory comprising: means for storing data; port means for transferring data to and from said memory in accordance with addressing sequences specified by an array transformation; said port means comprising an address generator for generating said addressing sequences as specified by said array transformation; network means for coordinating data transfers between said plurality of port means and said storing means; a data formatter for packing and unpacking data to and from said storing means; and a memory controller coupled to said address generator and said network means for controlling said address generator and said data formatter.

Claim 50

An intelligent memory comprising: means for storing data; port means for transferring data to and from said memory in accordance with addressing sequences specified by an array transformation; said port means comprising an address generator for generating said addressing sequences as specified by said array transformation; network means for coordinating data transfers between said plurality of port means and said storing means; a data formatter for packing and unpacking data to and from said storing means; and a memory controller coupled to said address generator and said network means for controlling said address generator and said data formatter.

Claim 51

The intelligent memory as recited in claim 39 wherein: said array transformation comprises a plurality of parameters for generating said addressing sequences for storing or accessing a data array; and said array comprises a vector, a matrix or a block of data.

Claim 52

The intelligent memory as recited in claim 39 wherein: said port means comprises at least three intelligent ports for transferring data to and from said memory, at least two of said ports operating in a read mode and at least one of said ports operating in a write mode; and said port means further comprises a direct memory access port for input-output data transfers.

Claim 53

The intelligent memory as recited in claim 39 wherein: said storing means comprises at least one random access memory and at least one read-only memory.

Claim 54

An address generator of an intelligent memory comprising: means for generating a plurality of row and column indices specified by an array transformation for addressing said memory.

Claim 55

An address generator of an intelligent memory comprising: means for generating a plurality of row and column indices specified by an array transformation for addressing said memory.

Claim 56

The address generator as recited in claim 43 wherein: said array transformation comprises a plurality of displacement and length parameters expressed relative to an initial reference point.

Claim 57

The address generator as recited in claim 43 wherein: said address generator comprises means for interpreting a boundary parameter of said array transformation for controlling the generating of addressing sequences outside a boundary of an array of data.

Claim 58

An address generator of an intelligent memory comprising: index generating means for generating a plurality of row and column indices specified by a plurality of parameters of an array transformation; and address translator means coupled to said index generating means for converting said row and column indices into a plurality of addresses.

Claim 59

An address generator of an intelligent memory comprising: index generating means for generating a plurality of row and column indices specified by a plurality of parameters of an array transformation; and address translator means coupled to said index generating means for converting said row and column indices into a plurality of addresses.

Claim 60

The address generator as recited in claim 46 wherein: said address generator comprises a multiplier coupled between said index generating means and said address translator means for multiplying a row index by a row length parameter of said array transformation during said address translation operation to generate said addresses.

Claim 61

The address generator as recited in claim 46 wherein: said array transformation specifies a boundary parameter for said address generator to operate in a plurality of modes comprising a wrap-around mode, a zero-fill mode and an ignore boundaries mode.

Claim 62

The address generator as recited in claim 46 wherein said index generator means comprises a wrap-around mode means for generating addresses on an opposite side of an array when a boundary of said array is reached by any one of said parameters of an array transformation.

Claim 63

The address generator as recited in claim 46 wherein: said index generator means comprises a zero-fill mode means for treating addresses generated outside the boundaries of an array as having zeroes stored therein.

Claim 64

The address generator as recited in claim 49 wherein: said index generator means comprises an ignore boundaries mode for addressing sequences to proceed through an array in said wrap-around mode ignoring all boundaries until a last address point is reached, returning to an initial address specified by an initial address parameter of said array transformation.

Claim 65

The address generator as recited in claim 50 wherein: said index generator means comprises an ignore boundaries mode for addressing sequences to proceed through an array in said zero-fill mode until a last address point is reached in said array, and continuing to generate said addressing sequences after said last address point.

Claim 66

An address generator of a memory comprising: an index generator means for generating a plurality of row and column indices, said index generator means being loaded with an initial address specified by an initial address parameter, delta 0, of an array transformation; means for storing in said index generator means a displacement parameter, delta 1, of said array transformation; means for storing in said address generator a length parameter, L1, of said array tmisforma- tion; means for incrementing said initial address in said index generator means with said displacement parameter a plurality of times equal to said length parameter; and means for translating said row and column indices into a plurality of addresses.

Claim 67

An address generator of a memory comprising: an index generator means for generating a plurality of row and column indices, said index generator means being loaded with an initial address specified by an initial address parameter, delta 0, of an array transformation; means for storing in said index generator means a displacement parameter, delta 1, of said array transformation; means for storing in said address generator a length parameter, L1, of said array tmisforma- tion; means for incrementing said initial address in said index generator means with said displacement parameter a plurality of times equal to said length parameter; and means for translating said row and column indices into a plurality of addresses.

Claim 68

The address generator as recited in claim 53 wherein: said index generator means comprises a row index generator and a column index generator.

Claim 69

An address generator of an intelligent memory comprising; a plurality of index generator means for generating a plurality of row and column indices, said index generator means being loaded with an initial address specifisd by an initial address parameter, delta 0, of an array transformation; means for storing in said plurality of index generator means for first displacement parameter, delta 1, and a second displacement parameter, delta 2, of said array transformation; means for storing in said address generator a first length parameter, L1, and a second length parameter, L2, of said array transformation; means for generating a first sequence of said row and column indices by incrementing said initial address in a first one of said index generator means with said first displacement parameter a plurality of times equal to said first length parameter; means for generating a second sequence of said row and column indices coupled to said first sequence generating means further comprising: (a) means for incrementing said initial address in a second one of said index generator means with said second displacement parameter; (b) means for loading said second one of said index generator means into said first one of said index generator means; (c) means for repeating said generating of said first sequence; and (d) said second sequence generating means controlling said incrementing means and said generating of said first sequence a plurality of times equal to said second length parameter; and means for translating said first sequence and said second sequence of said row and column indices into a plurality of addresses.

Claim 70

An address generator of an intelligent memory comprising; a plurality of index generator means for generating a plurality of row and column indices, said index generator means being loaded with an initial address specifisd by an initial address parameter, delta 0, of an array transformation; means for storing in said plurality of index generator means for first displacement parameter, delta 1, and a second displacement parameter, delta 2, of said array transformation; means for storing in said address generator a first length parameter, L1, and a second length parameter, L2, of said array transformation; means for generating a first sequence of said row and column indices by incrementing said initial address in a first one of said index generator means with said first displacement parameter a plurality of times equal to said first length parameter; means for generating a second sequence of said row and column indices coupled to said first sequence generating means further comprising: (a) means for incrementing said initial address in a second one of said index generator means with said second displacement parameter; (b) means for loading said second one of said index generator means into said first one of said index generator means; (c) means for repeating said generating of said first sequence; and (d) said second sequence generating means controlling said incrementing means and said generating of said first sequence a plurality of times equal to said second length parameter; and means for translating said first sequence and said second sequence of said row and column indices into a plurality of addresses.

Claim 71

The address generator as recited in claim 55 wherein: each of said plurality of index generator means comprises a row index generator and a column index generator for each of said sequence generating means.

Claim 72

An address generator of an intelligent memory comprising: a plurality of index generator means for generating a plurality of row and column indices, said index generator means being loaded with an initial address specified by an initial address parameter, delta 0, of an array transformation; means for storing in said plurality of index generator means a first displacement parameter, delta 1, a second displacement parameter, delta 2, and a third displacement parameter, delta 3, of said array transformation; means for storing in said address generator a first length parameter, L1, a second length parameter, L2, and a third length parameter, L3, of said array transformation; means for generating a first sequence of said row and column indices by incrementing said initial address in a first one of said index generator means with said first displacement parameter a plurality of times equal to said first length parameter; means for generating a second sequence of said row and column indices coupled to said first sequence generating means further comprising: (a) means for incrementing said initial address in a second one of said index generator means with said second displacement parameter; (b) means for loading said second one of said index generator means into said first one of said index generator means; (c) means for repeating said generating of said first sequence; and (d) said second sequence generating means controlling said second incrementing means and said generating of said first sequence a plurality of times equal to said second length parameter; means for generating a third sequence of said row and column indices coupled to said second sequence generating means further comprising: (a) means for incrementing said initial address in a third one of said index generator means with said third displacement parameter; (b) means for loading said third one of said index generator means into said second one of said index generator means; (c) means for repeating said generating of said first sequence and said second sequence of said row and column indices; and (d) said third sequence generating means controlling said third incrementing means and said generating of said second sequence a plurality of times equal to said third length parameter; and means for translating said first sequence, said second sequence and said third sequence of said row and column indices into a plurality of addresses.

Claim 73

An address generator of an intelligent memory comprising: a plurality of index generator means for generating a plurality of row and column indices, said index generator means being loaded with an initial address specified by an initial address parameter, delta 0, of an array transformation; means for storing in said plurality of index generator means a first displacement parameter, delta 1, a second displacement parameter, delta 2, and a third displacement parameter, delta 3, of said array transformation; means for storing in said address generator a first length parameter, L1, a second length parameter, L2, and a third length parameter, L3, of said array transformation; means for generating a first sequence of said row and column indices by incrementing said initial address in a first one of said index generator means with said first displacement parameter a plurality of times equal to said first length parameter; means for generating a second sequence of said row and column indices coupled to said first sequence generating means further comprising: (a) means for incrementing said initial address in a second one of said index generator means with said second displacement parameter; (b) means for loading said second one of said index generator means into said first one of said index generator means; (c) means for repeating said generating of said first sequence; and (d) said second sequence generating means controlling said second incrementing means and said generating of said first sequence a plurality of times equal to said second length parameter; means for generating a third sequence of said row and column indices coupled to said second sequence generating means further comprising: (a) means for incrementing said initial address in a third one of said index generator means with said third displacement parameter; (b) means for loading said third one of said index generator means into said second one of said index generator means; (c) means for repeating said generating of said first sequence and said second sequence of said row and column indices; and (d) said third sequence generating means controlling said third incrementing means and said generating of said second sequence a plurality of times equal to said third length parameter; and means for translating said first sequence, said second sequence and said third sequence of said row and column indices into a plurality of addresses.

Claim 74

The address generator as recited in claim 57 wherein: each of said plurality of index generator means comprises a row index generator and a column index generator for each of said sequence generating means.

Claim 75

An address generator of an intelligent memory comprising: a plurality of index generator means for generating a plurality of row and column indices, said index generator means being loaded with an initial address specified by an initial address parameter, delta 0, of an array transformation; means for storing in said plurality of index generator means a plurality of displacement parameters of said array transformation; means for storing in said address generator a plurality of length parameters of said array transformation, each of said length parameters defining a length for a corresponding one of said displacement parameters; means for generating a first sequence of said row and column indices by incrementing said initial address in a first one of said index generator means with a first one of said displacement parameters a plurality of times equal to said first length parameter; means for generating a second sequence of said row and column indices coupled to said first sequence generating means further comprising: (a) means for incrementing said initial address in a second one of said index generator means with a second one of said displacement parameters; (b) means for loading said second one of said index generator means into said first one of said index generator means; (c) means for repeating said generating of said first sequence; and (d) said second sequence generating means controlling said second incrementing means and said generating of said first sequence a plurality of times equal to said second one of said length parameters; means for generating a third sequence of said row and column indices coupled to said second sequence generating means further comprising: (a) means for incrementing said initial address parameter in a third one of said index generator means with a third one of said displacement parameters; (b) means for loading said third one of said index generator means into said second one of said index generator means; (c) means for repeating said generating of said first sequence and said second sequence of said row and column indices; and (d) said third sequence generating means controlling said third incrementing means and said generating of said second sequences a plurality of times equal to said third one of said length parameters; means for generating a fourth sequence of said row and column indices coupled to said third sequence generating means further comprising: (a) means for incrementing said initial address in a fourth one of said index generator means with a fourth one of said displacement parameters; (b) means for loading said fourth one of said index generator means into said third one of said index generator means; (c) means for repeating said generating of said first sequence, said second sequence and said third sequence of row and column indices; and (d) said fourth sequence generating means controlling said fourth incrementing means and said generating of said third sequence a plurality of times equal to said fourth one of said length parameters; and means for translating said first sequence and said fourth sequence of said row and column indices into a plurality of addresses.

Claim 76

An address generator of an intelligent memory comprising: a plurality of index generator means for generating a plurality of row and column indices, said index generator means being loaded with an initial address specified by an initial address parameter, delta 0, of an array transformation; means for storing in said plurality of index generator means a plurality of displacement parameters of said array transformation; means for storing in said address generator a plurality of length parameters of said array transformation, each of said length parameters defining a length for a corresponding one of said displacement parameters; means for generating a first sequence of said row and column indices by incrementing said initial address in a first one of said index generator means with a first one of said displacement parameters a plurality of times equal to said first length parameter; means for generating a second sequence of said row and column indices coupled to said first sequence generating means further comprising: (a) means for incrementing said initial address in a second one of said index generator means with a second one of said displacement parameters; (b) means for loading said second one of said index generator means into said first one of said index generator means; (c) means for repeating said generating of said first sequence; and (d) said second sequence generating means controlling said second incrementing means and said generating of said first sequence a plurality of times equal to said second one of said length parameters; means for generating a third sequence of said row and column indices coupled to said second sequence generating means further comprising: (a) means for incrementing said initial address parameter in a third one of said index generator means with a third one of said displacement parameters; (b) means for loading said third one of said index generator means into said second one of said index generator means; (c) means for repeating said generating of said first sequence and said second sequence of said row and column indices; and (d) said third sequence generating means controlling said third incrementing means and said generating of said second sequences a plurality of times equal to said third one of said length parameters; means for generating a fourth sequence of said row and column indices coupled to said third sequence generating means further comprising: (a) means for incrementing said initial address in a fourth one of said index generator means with a fourth one of said displacement parameters; (b) means for loading said fourth one of said index generator means into said third one of said index generator means; (c) means for repeating said generating of said first sequence, said second sequence and said third sequence of row and column indices; and (d) said fourth sequence generating means controlling said fourth incrementing means and said generating of said third sequence a plurality of times equal to said fourth one of said length parameters; and means for translating said first sequence and said fourth sequence of said row and column indices into a plurality of addresses.

Claim 77

The address generator as recited in claim 59 wherein: each of said plurality of index generator means comprises a row index generator and a column index generator for each of said sequence generating means.