Microprocessor assisted data block transfer apparatus

Claim 1

In a data processing system, an apparatus for controlling movement of a data block between a peripheral (40) and the data processing system, said apparatus character- ized by: a) a bus wherein said bus includes: i) an address bus (21); ii) a first data bus (A); and iii) a second data bus (B), wherein said peripheral is operatively connected to said second data bus; b) first memory means (RAM 30-1), operatively connected to said address bus and to said second data bus, for storing data; c) second memory means (ROM 30-31, IGC), operatively connected to said address bus and to said first data bus, for storing a plurality of sequences of dummy instructions in predetermined areas of said second memory means, said predetermined areas of said second memory means having corresponding buffer areas in said first memory means, each sequence of dummy instructions being determinative of the direction of the movement of the data between the peripheral and the data processing system and wherein said first memory means and said second memory means corresponds to a first memory area and a second memory area within a total predefined memory space, each memory location within the total memory space being defined by a unique memory space address; d) processor means (10), operatively connected to said address bus and to said first data bus, and further operatively connected to said peripheral, for fetching an instruction, in response to a control signal from said peripheral, from a preselected one of said sequences of dummy instructions whereby the address of said instruction is placed on the address bus thereby specifying a corresponding location of the corresponding buffer area in said first memory means; e) switch means (25), operatively connected to said first data bus and said second data bus, for disconnecting said first data bus from said second data bus in response to an enable signal, thereby inhibiting the movement of data between said first data bus and said second data bus; and f) logic means (30-2), operatively connected to said first memory means, said second memory means, said processor means, said switch means, and said peripheral, for generating at least one control signal to enable at least one of said first memory means, said second memory means, said switch means, and said peripheral in response to the memory area addressed by said processor means, such that the fetching of said instruction by said processor means from one of said sequences of dummy instructions causes data to be transferred between said peripheral and said data processing system.