EP0211367A2
Expired / Lapsed
EP
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Doping for low capacitance amorphous silicon field effect transistor
Assignee: General Electric Co
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Filing: 1986-07-28
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Granted: —
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Expires: 2006-07-28
Abstract
Abstract An amorphous silicon thin film FET is doped and structured to be particularly useful for use in liquid crystal display circuits. In particular, critical FET dimensions are provided along with doping levels and locations which permit optimal reduction of source to gate capacitance, while at the same time, preventing the occurrence of large contact voltage drops. Critical dimensions include active channel length, source-gate overlap, and amorphous silicon thickness. A critical relationship is established amongst these parameters and amorphous silicon doping levels.
Inventors
- 👤 William Weidman Piper
- 👤 George Edward Possin
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 19:27
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6757; H10D30/6704; H10D30/6713; H10D30/6729; H10D30/673; H10D30/6732; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6746
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
172 words
An amorphous silicon thin film field effect transistor, particularly for use in liquid crystal display devices, said field effect transistor comprising: an insulating substrate; a gate electrode disposed on said insulating substrate; an insulating layer disposed over said gate electrode; an amorphous silicon layer disposed over said insulating layer, said amorphous silicon layer possessing a thickness t; a drain electrode disposed on said amorphous silicon layer so as to partially overlie said gate electrode; a source electrode disposed on said amorphous silicon layer so as to define a channel region of length L in said amorphous silicon layer, said channel region extending in said amorphous silicon layer between said source electrode and said drain electrode, said source electrode overlying said gate electrode by a distance d; said distance d being given approximately by cu e/ (2La), where c is the gate capacitance per unit area, µ e is the effective electron mobility in the amorphous silicon layer and a is between about 5 amperes/cm2/volt2 and 50 ampere/cm 2 / volt 2 .
Claim 2
Dependent Claim
172 words
An amorphous silicon thin film field effect transistor, particularly for use in liquid crystal display devices, said field effect transistor comprising: an insulating substrate; a gate electrode disposed on said insulating substrate; an insulating layer disposed over said gate electrode; an amorphous silicon layer disposed over said insulating layer, said amorphous silicon layer possessing a thickness t; a drain electrode disposed on said amorphous silicon layer so as to partially overlie said gate electrode; a source electrode disposed on said amorphous silicon layer so as to define a channel region of length L in said amorphous silicon layer, said channel region extending in said amorphous silicon layer between said source electrode and said drain electrode, said source electrode overlying said gate electrode by a distance d; said distance d being given approximately by cu e/ (2La), where c is the gate capacitance per unit area, µ e is the effective electron mobility in the amorphous silicon layer and a is between about 5 amperes/cm2/volt2 and 50 ampere/cm 2 / volt 2 .
Claim 3
Dependent Claim
16 words
The transistor of claim 1 in which said thickness t is less than approximately 300 nm.
Claim 4
Dependent Claim
14 words
The transistor of claim 1 in which said thickness t is approximately 150 nm..
Claim 5
Dependent Claim
21 words
The transistor of claim 1 in which lie is between between approximately 0.5 cm 2 /volt and 0.8 cm 2 volt.
Claim 6
Dependent Claim
17 words
The transistor of claim 1 in which c is approximately 4 x 10 -8 farads/cm 2 .
Claim 7
Dependent Claim
17 words
The transistor of claim 1 in which said overlap distance d is less than approximately 1 micron.
Claim 8
Dependent Claim
27 words
The transistor of claim 1 in which said amorphous silicon layer is phosphorous doped to achieve a room temperature conductivity of approximately 2 x 10 -5 mho/cm.
References Cited (Backward Citations)
No citation records indexed.
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