EP0218406A2
Expired / Lapsed
EP
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Sampling clock generation circuit
Assignee: Seiko Instruments Inc
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Filing: 1986-09-22
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Granted: —
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Expires: 2006-09-22
Abstract
Abstract A sampling clock generation circuit comprises a phase comparison circuit (1), a loop filter (2), a voltage control oscillator (3) and a first frequency divider (5). A horizontal sync signal or composite sync signal (8) of the video signal is used as a reference input signal of the phase comparison circuit (1).
Inventors
- 👤 Fumihiro Seiko Instruments & Electronics Tanaka
- 👤 Kenichi Seiko Instruments & Electroni Matsushima
- 👤 Yoshio Seiko Instruments & Electronics Shimada
- 👤 Kaneo Seiko Instruments & Electronics Yamaguchi
- 👤 Shinya Seiko Instruments & Electronics Watanabe
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 01:33
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H04; H04N; H04N5/00; H04N5/14; H04N5/76; H04N5/91; H04N5/93; H04N5/932
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
57 words
A sampling clock generation circuit characterised by comprising: a phase comparison circuit (1), a loop filter (2), a voltage controlled oscillator (3), and a first frequency divider (5) wherein, in operation, a horizontal sync signal or a composite sync signal (8) of a video signal is used as a reference input of said phase comparison circuit (1).
Claim 2
Dependent Claim
57 words
A sampling clock generation circuit characterised by comprising: a phase comparison circuit (1), a loop filter (2), a voltage controlled oscillator (3), and a first frequency divider (5) wherein, in operation, a horizontal sync signal or a composite sync signal (8) of a video signal is used as a reference input of said phase comparison circuit (1).
Claim 3
Dependent Claim
32 words
A sampling clock generation circuit as claimed in claim 1 characterised by a second frequency divider (4) with an arbitrary division ratio disposed at the output of said voltage controlled oscillator (3).
Claim 4
Dependent Claim
25 words
A sampling clock generation circuit as claimed in claim 2 characterised in that said second frequency divider (4) is arranged to produce a sampling clock.
Claim 5
Dependent Claim
61 words
A sampling clock generation circuit as claimed in claim 2 or 3, characterised in that a video signal clock number of one period of said horizontal sync signal or a multiple of said video signal clock number is used as a frequency division ratio of a frequency division circuit comprising said first frequency divider (5) and said second frequency divider (4).
Claim 6
Dependent Claim
43 words
A sampling clock generation circuit as claimed in any preceding claim characterised in that said phase comparison circuit (1) is arranged to effect comparison at the front edge of said horizontal sync signal or a horizontal sync element of said composite sync signal.
Claim 7
Dependent Claim
40 words
A sampling clock generation circuit as claimed in any preceding claim characterised by means (11,12) for inhibiting operation of said phase comparison circuit (1) when a vertical sync element of said composite sync signal of said video signal is inputted.
Claim 8
Dependent Claim
142 words
A sampling clock generation circuit characterised by comprising a phase comparison circuit (1) having first, second and third terminals, a loop filter (2) connected to an output terminal of said phase comparison circuit (1), a voltage control oscillator (3) connected to an output terminal of said loop filter (2) for generating a sampling clock to sample a video signal, the second frequency divider (4) connected to an output terminal of said voltage controlled oscillator (3), and a first frequency divider (5) connected to an output terminal of said second frequency divider (4) and having its output connected to the first input of the phase comparator circuit (1), said second input terminal of the phase comparator circuit, in operation, receiving a horizontal sync signal or a composite sync signal (8) and receiving a vertical sync signal (6) at said third input terminal thereof.
Claim 9
Dependent Claim
142 words
A sampling clock generation circuit characterised by comprising a phase comparison circuit (1) having first, second and third terminals, a loop filter (2) connected to an output terminal of said phase comparison circuit (1), a voltage control oscillator (3) connected to an output terminal of said loop filter (2) for generating a sampling clock to sample a video signal, the second frequency divider (4) connected to an output terminal of said voltage controlled oscillator (3), and a first frequency divider (5) connected to an output terminal of said second frequency divider (4) and having its output connected to the first input of the phase comparator circuit (1), said second input terminal of the phase comparator circuit, in operation, receiving a horizontal sync signal or a composite sync signal (8) and receiving a vertical sync signal (6) at said third input terminal thereof.
Claim 10
Dependent Claim
17 words
A recording apparatus characterised by having a sampling clock generation circuit as claimed in any preceding claim.
Claim 11
Dependent Claim
78 words
In a recording apparatus (60) for receiving video signals (51) for displaying image data on a display device (50) and recording said image data, a sampling clock generation circuit (63) having a phase comparison circuit (1), a loop filter (2), a voltage controlled oscillator (3) and a first frequency divider (5) wherein a horizontal sync signal or composite sync signal (8) of said video signal is used as a reference input signal of said phase comparison circuit (1).
Claim 12
Dependent Claim
78 words
In a recording apparatus (60) for receiving video signals (51) for displaying image data on a display device (50) and recording said image data, a sampling clock generation circuit (63) having a phase comparison circuit (1), a loop filter (2), a voltage controlled oscillator (3) and a first frequency divider (5) wherein a horizontal sync signal or composite sync signal (8) of said video signal is used as a reference input signal of said phase comparison circuit (1).
References Cited (Backward Citations)
No citation records indexed.
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