Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
70 words
A semiconductor programmable memory device in which a checker board pattern is written in a memory matrix for checking its operation, said device comprising; a first means for selecting all of the word lines (WL) at the same time; a second means for selecting all of the bit lines (BL) at the same time; and a third means for selecting every other one word lines (WL) at the same time.
Claim 2
Dependent Claim
70 words
A semiconductor programmable memory device in which a checker board pattern is written in a memory matrix for checking its operation, said device comprising; a first means for selecting all of the word lines (WL) at the same time; a second means for selecting all of the bit lines (BL) at the same time; and a third means for selecting every other one word lines (WL) at the same time.
Claim 3
Dependent Claim
21 words
A semiconductor programmable memory device according to claim 1, wherein said first means and second means are combined into one means.
Claim 4
Dependent Claim
21 words
A semiconductor programmable memory device according to claim 1, wherein said first means and third means are combined into one means.
Claim 5
Dependent Claim
21 words
A semiconductor programmable memory device according to claim 1, wherein said second means and third means are combined into one means.
Claim 6
Dependent Claim
23 words
A semiconductor programmable memory device according to claim 1, wherein said first means, second means and third means are combined into one means.
Claim 7
Independent Claim
145 words
A method to write a checker board pattern in a memory matrix of a semiconductor programmable memory device comprising following steps in sequence, step A): selecting all of the word lines and all of the bit lines at the same time, then erasing all bits in said memory matrix, and write a data "1" to all of the memory cells; step B); selecting all of the word lines at the same time, and writing to all of the bit lines alternately data of "0" and "1". step (C): selecting the word lines every other one at the same time, and writing to all of the bit lines a datum "0"; and step (D): selecting the word lines every other one at the same time, and writing to all of the bit lines an inverse data of the step (B), namely "1" "0" "1" "0" ···.
Claim 8
Independent Claim
145 words
A method to write a checker board pattern in a memory matrix of a semiconductor programmable memory device comprising following steps in sequence, step A): selecting all of the word lines and all of the bit lines at the same time, then erasing all bits in said memory matrix, and write a data "1" to all of the memory cells; step B); selecting all of the word lines at the same time, and writing to all of the bit lines alternately data of "0" and "1". step (C): selecting the word lines every other one at the same time, and writing to all of the bit lines a datum "0"; and step (D): selecting the word lines every other one at the same time, and writing to all of the bit lines an inverse data of the step (B), namely "1" "0" "1" "0" ···.