EP0223621A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor memory device having a circuit for compensating for discriminating voltage variations of a memory cell
Assignee: Fujitsu Ltd
•
Filing: 1986-08-29
•
Granted: —
•
Expires: 2006-08-29
Abstract
Abstract A semiconductor memory device capable of compensating for variation in a discriminating voltage of a memory cell comprising a memory cell (MC) and a gate circuit (Qs) for coupling the memory cell to a bit line (WL). The device has a precharge circuit for precharging the bit line pair to a predetermined resultant precharge voltage in a reset state. The precharge circuit (Q5, Q6, Q4, Cps, Q7) precharges a bit line pair with the resultant precharge voltage (Vcc/2 + α) obtained by adding a compensating voltage to a precharge voltage in the reset state. The compensating voltage is adapted to compensate for variation in a memory cell discriminating voltage based on variation in a memory cell voltage caused by capacitive coupling of a word line to a memory capacitor due to a parasitic capacitance of a gate circuit in the active state, and the precharge voltage is adapted to optimize the memory cell discriminating voltage when it is assumed that the parasitic capacitance is not present.
Inventors
- 👤 Masao Nakano
- 👤 Yoshihiro Takemae
- 👤 Tomio Nakano
- 👤 Shigeki Nozaki
- 👤 Kimiaki Sato
- 👤 Nobumi Kodama
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 21:29
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4099; G11C11/4094
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
263 words
A semiconductor memory device having a circuit for compensating for a discriminating voltage of a memory cell, comprising: a bit line pair consisting of first and second bit lines; a memory cell comprising a memory capacitor for storing data and a gate circuit capable of coupling the memory capacitor to the first bit line of the bit line pair; a word line, connected to the gate circuit, for energizing and deenergizing the gate circuit to control coupling and decoupling of the memory cell to and from the first bit line; a sense amplifier connected to the bit line pair, which sense amplifier being adapted to sense and amplify a voltage at the first bit line by using a precharge voltage of the second bit line as a reference voltage in an active state of the semiconductor memory device; and a precharge circuit for precharging the bit line pair to a predetermined resultant precharge voltage in a reset state of the semiconductor memory device, wherein the precharge circuit precharges the bit line pair with the resultant precharge voltage obtained by adding a compensating voltage to a precharge voltage in the reset state, the compensating voltage being adapted to compensate for variation in a memory cell discriminating voltage based on variation in a memory cell voltage caused by capacitive coupling of the word line to the memory capacitor due to a parasitic capacitance of the gate circuit in the active state, and the precharge voltage being adapted to optimize the memory cell discriminating voltage when it is assumed that the parasitic capacitance is not present.
Claim 2
Dependent Claim
263 words
A semiconductor memory device having a circuit for compensating for a discriminating voltage of a memory cell, comprising: a bit line pair consisting of first and second bit lines; a memory cell comprising a memory capacitor for storing data and a gate circuit capable of coupling the memory capacitor to the first bit line of the bit line pair; a word line, connected to the gate circuit, for energizing and deenergizing the gate circuit to control coupling and decoupling of the memory cell to and from the first bit line; a sense amplifier connected to the bit line pair, which sense amplifier being adapted to sense and amplify a voltage at the first bit line by using a precharge voltage of the second bit line as a reference voltage in an active state of the semiconductor memory device; and a precharge circuit for precharging the bit line pair to a predetermined resultant precharge voltage in a reset state of the semiconductor memory device, wherein the precharge circuit precharges the bit line pair with the resultant precharge voltage obtained by adding a compensating voltage to a precharge voltage in the reset state, the compensating voltage being adapted to compensate for variation in a memory cell discriminating voltage based on variation in a memory cell voltage caused by capacitive coupling of the word line to the memory capacitor due to a parasitic capacitance of the gate circuit in the active state, and the precharge voltage being adapted to optimize the memory cell discriminating voltage when it is assumed that the parasitic capacitance is not present.
Claim 3
Dependent Claim
77 words
A semiconductor memory device according to claim l, wherein the precharge circuit comprises: a second gate circuit for short-circuiting between the first and second bit lines in the reset state to supply to the bit line pair the precharge voltage for optimizing the memory cell discriminating voltage when it is assumed that the parasitic capacitance is not present; and a compensating circuit for adding, to the precharge voltage obtained by the second gate circuit, the compensating voltage.
Claim 4
Dependent Claim
147 words
A semiconductor memory device according to claim 2, wherein the compensating circuit comprises: a compensating capacitor for storing a charge corresponding to the variation in the compensating voltage for compensating the memory cell discriminating voltage based on the variation in the memory cell voltage caused by the capacitive coupling of the word line to the memory capacitor due to the parasitic capacitance of the gate circuit upon activation of the memory cell by means of the word line; a second gate circuit for supplying the charge corresponding to the compensating voltage to the compensating capacitor in the active state; and a third gate circuit for supplying the charge corresponding to the compensating voltage from the compensating capacitor to the bit line pair in the reset state, thereby compensating for variation in the memory cell discriminating voltage based on the parasitic capacitance and thereby optimizing the discriminating voltage.
Claim 5
Dependent Claim
33 words
A semiconductor memory device according to claim 3, wherein the compensating circuit is constituted to be capable of compensating for a decrease in the memory cell discriminating voltage based on the parasitic capacitance.
Claim 6
Dependent Claim
33 words
A semiconductor memory device according to claim 3, wherein the compensating circuit is constituted to be capable of compensating for an increase in the memory cell discriminating voltage based on the parasitic capacitance.
Claim 7
Dependent Claim
60 words
A semiconductor memory device according to claim 3, wherein the compensating circuit further comprises a fourth gate circuit for charging the compensating capacitor in the active state, which is alternatively operated with the second gate circuit, the compensating circuit being capable of compensating for both a decrease and increase in the memory cell discriminating voltage based on the parasitic capacitance.
Claim 8
Dependent Claim
49 words
A semiconductor memory device according to any one of claims l to 6, wherein the precharge circuit further comprises a high-impedance resistance voltage divider for supplying the resultant precharge voltage to the bit line pair in the reset state for a provision of a long period of reset time.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.